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Implementation of a Single Channel Automatic Identification System (AIS) on a Field Programmable Gate Array (FPGA)

Patel, Pranav R.
http://rave.ohiolink.edu/etdc/view?acc_num=dayton1372511698

Abstract Details

2013, Master of Science (M.S.), University of Dayton, Electrical Engineering.
Automatic Identification System (AIS) plays an important role to track maritime vessels. In a world of Somali pirates hijacking maritime vessels and U.S. Navy destroyers slamming into Supertankers, AIS is an inexpensive low power wireless communication sensor solution used to identify and exchange information (GPS, heading, speed, etc.) with other maritime vessels. This research project is an implementation of a single channel Automatic Identification System (AIS) on a Field Programmable Gate Array (FPGA) chip used on common military signal intelligence systems. Unlike conventional AIS receivers, the design uses commonly existing components that are found in military signal intelligence systems. The AIS receiver algorithms developed in this project can successfully detect the AIS signal, demodulate the Gaussian Minimum Shift Keying (GMSK) modulation, decode, and encode the messages in National Marine iv Electronics Association (NMEA 0813) standard format to be compatible with other maritime equipment.
Monish Chatterjee (Committee Chair)
Eric Balster (Committee Member)
Robert McTasney (Committee Member)
95 p.
Computer Engineering; Electrical Engineering; Engineering
Automatic Identification System; AIS

Recommended Citations

Citations

  • Patel, P. R. (2013). Implementation of a Single Channel Automatic Identification System (AIS) on a Field Programmable Gate Array (FPGA) [Master's thesis, University of Dayton]. OhioLINK Electronic Theses and Dissertations Center. http://rave.ohiolink.edu/etdc/view?acc_num=dayton1372511698

    APA Style (7th edition)

  • Patel, Pranav. Implementation of a Single Channel Automatic Identification System (AIS) on a Field Programmable Gate Array (FPGA). 2013. University of Dayton, Master's thesis. OhioLINK Electronic Theses and Dissertations Center, http://rave.ohiolink.edu/etdc/view?acc_num=dayton1372511698.

    MLA Style (8th edition)

  • Patel, Pranav. "Implementation of a Single Channel Automatic Identification System (AIS) on a Field Programmable Gate Array (FPGA)." Master's thesis, University of Dayton, 2013. http://rave.ohiolink.edu/etdc/view?acc_num=dayton1372511698

    Chicago Manual of Style (17th edition)

dayton1372511698
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© 2013, all rights reserved.
This open access ETD is published by University of Dayton and OhioLINK.