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Degree

MS, University of Cincinnati, Engineering : Computer Engineering, 2001.

Abstract

The traditional approach to design validation has been to use implementation-based testing techniques. These techniques select test data based on the information obtained from the implementation. They focus on the actual behavior of the implementation, and tend to ignore its intended behavior. Validating a system design using specification-based testing techniques has several advantages over the implementation-based techniques. Selecting test data from the specifications enables testing intended behavior as well as actual functionality. Testing the implementation with respect to its specification ascertains that the implementation satisfies its requirements. This is called validation of the implementation, where we try to establish whether we have implemented the correct component. We thus try to ensure that the correct system has been built. In this thesis, we present a methodology for generating test scenarios and test vectors from Rosetta specifications. The primary objective of the Design Verification Test Generator (DVTG) is the automatic generation of test vectors from requirements representations. The functional requirements for components are represented in a traditional axiomatic style using Rosetta facets. The DVTG tool "walks through" a Rosetta specification, and generates input criteria and acceptance criteria, for the input and output parameters respectively. These classes of test vectors, known as test scenarios, are represented as a Rosetta facet. The input criteria are then combined with test requirements specified in Rosetta, to generate abstract test vectors. The abstract test vectors, represented in Rosetta, can be directly translated into concrete test vectors that are used as specific inputs to simulation runs. The outputs generated during these runs can be verified against the acceptance criteria to validate the implementation. In this thesis, we also demonstrate the generation of concrete test vectors by transforming the abstract vectors into WAVES test vectors suitable for VHDL simulation.

Keywords

DVTG; Automated Test Vector Generation; Specification-Based Testing from Rosetta

Advisor

Dr. Perry Alexander

Pages

85p.

Document number: ucin994691304
Permalink: http://rave.ohiolink.edu/etdc/view?acc_num=ucin994691304

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