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Degree

MS, University of Cincinnati, Engineering : Computer Engineering, 2009.

Abstract

The bottle neck problem of “erase before write” in NAND-based flash memory and its lifetime are the most important issues in today's flash design. This paper offers different approaches on improving the lifetime and performance of current generation solid state disks including cache algorithms and SRAM-based log buffer scheme with careful study and discussion on several design issues as well as the control logic of flash memory array. Both block level associative sector translation scheme and fully associative sector translation scheme are discussed in detail in the paper.

Subject Headings

Engineering

Keywords

Log block; LOG BUFFER; FLASH; block and data; LOG; cache; block

Committee / Advisors

Yiming Hu (Committee Chair)
Carla Purdy (Committee Member)
Karen Davis (Committee Member)

Pages

71p.

Document number: ucin1232126802
Permalink: http://rave.ohiolink.edu/etdc/view?acc_num=ucin1232126802

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