Display Full Text | Download Full Text
38.57 MB PDF file

Degree

MS, University of Cincinnati, Engineering : Computer Engineering, 2002.

Abstract

The iPACE-V1 (Image Processing Adaptive Computing Engine) is a portable, reconfigurable hardware platform, designed in the Digital Design Environments Laboratory at the University of Cincinnati. iPACE-V1 was specifically designed for real time, in-field image processing applications. Adaptive computing systems can be broadly defined as those systems which can modify their digital hardware to match the requirements of an application at hand. Field Programmable Gate Arrays (FPGA) are essential building blocks of such systems. iPACE-V1 has three Xilinx Virtex FPGAs: one houses the controller module, another acts as the main user programmable module and the data capture module is implemented in the last one. A maximum of 800,000 logic gates are available for computing in the form of FPGAs. Furthermore, 4 Mbytes of ZBT (Zero Bus turnaround) SRAM is interfaced. In addition to this, the board has a maximum of 1 Gigabytes SDRAM capacity. For non volatile data storage we have provided 4 Mbytes of FLASH ROM. Two serial ports along with a USB port are also provided. A camera is attached which provides video data and a small LCD is interfaced for image output. Every effort was made to incorporate as many debugging features, as possible: programmable clock, observable memories, partial reconfiguration and FPGA read-back are some features which top this list. Several controller cores have been written for various subsystems in iPACE-V1. These cores enable the user to efficiently exploit the available resources. This thesis discusses the hardware architecture of iPACE-V1 along with the VHDL controller cores. We also show the functional correctness and effectiveness of iPACE-V1. We have developed two demonstration examples for iPACE-V1: A frame grabber and a background elimination application. The frame grabber is implemented to demonstrate the functional correctness of the hardware. Whereas, the background elimination application is more performance oriented and is used to show the effectiveness of this architecture for realtime image processing.

Subject Headings

Computer Science

Keywords

reconfigurable computing; adaptive computing; FPGAs; mobile computing; image processing

Advisor

Dr. Ranga Vemuri

Pages

139p.

Document number: ucin1025721991
Permalink: http://rave.ohiolink.edu/etdc/view?acc_num=ucin1025721991

This ETD has been downloaded 378 times (through March 2013)