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An automatic test pattern generation in the logic gate level circuits and MOS transistor circuits at Ohio University

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Degree
Master of Science (MS), Ohio University, Electrical Engineering (Engineering), .
Keywords
Automatic Test Pattern Generation; Logic Gate Level Circuits; MOS Transistor Circuits; Ohio University
Advisor
Janusz A. Starzyk
Pages
166p.

Document number: ohiou1183139647
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This ETD has been downloaded 292 times (through March 2013)