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Degree

Master of Science, University of Akron, Electrical Engineering, 2012.

Abstract

In this thesis, a 10-bit dual plate sampling capacitor DAC with reduced offset internal reference voltage generation is proposed. Instead of using the conventional two element switched capacitor circuit that consists of the charge sampling and summing capacitor, the proposed scheme performs the identical operation using a single capacitor without affecting the conversion speed. As a result, the capacitor area can be considerably reduced compared to conventional capacitive DACs, which eventually leads to power saving due to amplifier effective load reduction and feedback factor improvement. The auto-zero internal reference voltage generator replaces the resistive ladder voltage divider with two unit capacitors, reference amplifiers, and several switches which further reduces the area of the DAC. In addition, the effect of major non-idealities including reference voltage mismatch, capacitor mismatch, and parasitic capacitance are analyzed. The proposed DAC is implemented using CMOS 0.35µm technology with core size of 0.11mm2. The maximum INL and DNL measured in a fabricated circuit were 0.67 LSB and 0.33 LSB, respectively.

Subject Headings

Electrical Engineering; Engineering

Keywords

Dual plate sampling; switched-capacitor circuit; digital-to-analog converter; auto-zero technique; DAC; display driver; 10-bit; reference generator

Committee / Advisors

Dr. Kye-Shin Lee (Advisor)
Dr. Joan Carletta (Committee Member)
Dr. Robert Veillette (Committee Member)

Pages

121p.

Document number: akron1349294825
Permalink: http://rave.ohiolink.edu/etdc/view?acc_num=akron1349294825

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