Department: Engineering and Applied Science: Computer Engineering ![[clear]](close-x.png "Remove this limiter")
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1.
Agrawal, Natwar.
A Generic Synthesizable HDL Platform for Network on Chip(GSHNoC).
Degree: MS, Engineering and Applied Science: Computer Engineering, 2011, University of Cincinnati
► Multi-cores processor architecture has proven to be the solution of diminishing return…
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▼ Multi-cores processor architecture has proven to be the solution of diminishing return in processing power when the frequency of uniprocessors is further increased. Because of the bandwidth limit, the current Common Bus communication architecture becomes inefficient if the number of cores in a processor increases more than a handful.New on chip communication architectures has been explored and packet switch Network on Chip has come out to be the future of multi-core interconnects architectures. The performance of the NoC architecture is sensitive to the topology, queue sizes, cache size and its associativity, arbitration scheme, flow control etc. Hence, to study the tradeoffs between area, timing and performance in NoCs is time consuming. The software platform available to run experiments on NoC architectures has many limitations such as •The time to run benchmarks on the big NoC configurations is huge (in days) making it infeasible to run experiments. •It does not give accurate information about the cost function such as area, timing and power. •It does give the feasibility of hardware implementation for these architectures. The freely available hardware platform tool is very specific for a particular application and does not support re-configurability and detailed simulation. The proposed Generic Synthesizable HDL (Hardware descriptive platform) Platform for NoCs provides a platform for the multi-core NoC architecture experimentation with the following features:- •It provides support for Common bus, NoC, hybrid NoCs and hybrid NoC with core migration architectures with customizable parameters such as data width, address width, queue sizes, cache sizes etc. •Speeds up the simulation if implemented in hardware compared to any software platform. •Other NoC architectures can be implemented by reusing the components used in the design. •Gives the accurate estimation of area, timing and performance. •This can be implemented in any hardware platform such as FPGA, ASIC or Palladium. •The simulation is more detailed compared to other software or hardware platforms. •The interface for the design components is generic so that it can be replaced by other application specific components, for example high end processor replacing the processor cores used. The above platform has been implemented, synthesized and simulated for various NoC configurations.
Advisors/Committee Members: Vemuri, Ranganadha.
Subjects: Computer Engineering
Keywords: NoC HDL Platform; NoC Experimental Platform; GSHNoC; Network on Chip Platform; Mulitore Architecture HDL Platform; Natwar Agrawal
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2.
Ahmed, Mohammad Nasar.
Using Agent-based Modeling and Simulation to Study the Structural Behavior of DNA.
Degree: MS, Engineering and Applied Science: Computer Engineering, 2011, University of Cincinnati
► Agent-based modeling and simulation (ABMS) is a powerful tool for modeling phenomena…
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▼ Agent-based modeling and simulation (ABMS) is a powerful tool for modeling phenomena at the molecular level. ABMS can be applied to model a system that can simulate the structural behavior of DNA. The system we intend to model needs to be powerful enough to simulate the well-known laboratory experiments on DNA by Adelman. This system should also be able to simulate the properties of emerging nanodevices. The system must demonstrate the basic structural behavior of DNA such as synthesis of double stranded DNA, formation of branched structures and separation of double stranded DNA. The system aimed to design must be able to be extended to be used to model the DNA self-assembly required in the process of fabrication of nanocircuits. Here we describe our work on developing basic building blocks for the system that can implement complex DNA models such as Adelman’s experiment and the experiments we conducted to validate our work. The experiments were chosen to cover the basic behavioral aspects of DNA such as synthesis of double stranded DNA, time taken for synthesizing DNA and separation of double stranded DNA.
Advisors/Committee Members: Purdy, Carla.
Subjects: Computer Engineering
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3.
Balakumar, Nikhil.
A Computational Model of Neuronal Cluster Activity.
Degree: MS, Engineering and Applied Science: Computer Engineering, 2012, University of Cincinnati
► Explaining the processing of information in the brain at its most simple…
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▼ Explaining the processing of information in the brain at its most simple level (the firing and transmission of electrical signals) is of immense importance to science. However due to the complexity and size of the brain, scientists often focus on smaller regions. Understanding the methods by which the synchronized firing of small clusters of neurons can create complex phenomena such as working memory, discriminatory selection and other commonly seen functions of the brain forms the basis for understanding advanced processes in the brain. Neuronal cultures show remarkable properties of self-organization and synchronization when allowed to grow without interference. Clusters of neurons are seen to form without any external help in these neuronal cultures. These clusters proceed to form a network of interconnects which allows the synchronized firing of action potentials. This synchronization is at two levels, synchronized bursting events (SBEs) of action potentials within each cluster, as well as the synchronization of these SBEs that occur in connected clusters. A computational model of the electrical oscillations in neuronal network representing a single cluster of neurons, as well as two connected clusters is provided in this thesis. This model allows us to examine the different factors that cause synchronization as well to show the extent of information processing that is possible in a randomly generated network of clusters. The model generated shows that the delay between clusters plays a critical role in maintaining sustained reverberations within a network. The model shows two clear bifurcation points as delay is varied that transition the network into three different regions of operation. It also shows that the network can selectively remember patterns of input and sustain these patterns for as long as needed. This type of pattern storage is a viable model to explain working memory and processes similar to it.
Advisors/Committee Members: Minai, Ali.
Subjects: Computer Engineering
Keywords: Neuronal Networks; Synchronization; Simulation; Izhikevich Model; Oscillation; Network Activity
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4.
Buttar, Harmandeep Kaur.
Multi Robot Motion Planning with Communication.
Degree: MS, Engineering and Applied Science: Computer Engineering, 2012, University of Cincinnati
► A successful motion planning algorithm was designed and implemented on multiple high…
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▼ A successful motion planning algorithm was designed and implemented on multiple high performance KheperaIII robots. 2 KheperaIII robots finds a dynamic path from the specified source to the targeted destination avoiding collisions in an unpredictable environment processing real-time data exchanged within robots by distributed communication on a well-spaced grid where boundaries are used as landmarks ascertained by the infrared sensors. Distributed communication was implemented by implementing server and client on every robot in the system with the help of multi-threads. This algorithm hence, is successful implementation in the field of motion planning and coordination with autonomous robots. Also in this thesis, is explained the centralized and decoupled behavior of the motion planning algorithms on the multi robots. The implementation of the algorithm over KheperaIII robots aimed at representing the successfulness of this technique in practical cases, as the work in this field is still relatively new.
Advisors/Committee Members: Bhatnagar, Raj.
Subjects: Computer Engineering
Keywords: Multi; Robot; Motion; Planning; Distributed; Communication
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5.
Chakkaravarthy, Manoj.
BDD Based Synthesis Flow for Design of DPA Resistant Cryptographic Circuits.
Degree: MS, Engineering and Applied Science: Computer Engineering, 2012, University of Cincinnati
► The revolution brought by the advancement in Integrated Circuits (IC) technology has…
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▼ The revolution brought by the advancement in Integrated Circuits (IC) technology has resulted in an exponential increase in the use of smartcards and other cryptographic devices for several security-centric applications like digital signatures, identification and secure communication. This growing dependency on electronic devices for critical applications has led to increased sophistication of hardware attacks on ICs, resulting in the need for effective hardware implementation of cryptographic algorithms. Cryptographic algorithms, in spite of being mathematically secure, lose their potency when implemented in hardware due to data leakage at the hardware level through channels like power consumption, timing delay and Electromagnetic emanation. Attacks based on such leakage channels are commonly referred to as Side Channel Attacks (SCA). Differential Power Analysis (DPA) is a sophisticated SCA method that breaks a cryptographic circuit by correlating the power consumption and the applied inputs. DPA based attacks exploit a fundamental weakness in current ASIC design methodologies (SCMOS), where the power consumption is dependent on the applied inputs. Several countermeasures have been proposed at the circuit level to prevent DPA attacks. Secure Differential Multiplexer based Logic using Pass Transistors (SDMLp) is one such countermeasure designed at Digital Design and Environments Lab at University of Cincinnati. In this thesis, we propose a Synthesis Flow for DPA resistant circuits using Binary Decision Diagrams for the SDMLp logic style. Using the proposed design flow, we achieve an average area reduction of 35% and power saving of 30% albeit with a delay penalty of 20% compared to existing secure libraries. We also show that the maximum instantaneous current variance (security metric) is 40 times better for the proposed synthesis flow than existing synthesis techniques for other secure libraries (WDDL).
Advisors/Committee Members: Vemuri, Ranganadha.
Subjects: Computer Engineering
Keywords: Hardware Security; Differential Power Analysis (BDD); Side channel Attacks (SCA); Cryptographic Circuits; BDD Based Synthesis Flow; DPA Countermeasures
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6.
Child, Ryan.
Performance and Power Optimization of Parallel Discrete Event Simulations Using DVFS.
Degree: MS, Engineering and Applied Science: Computer Engineering, 2012, University of Cincinnati
► Parallel Discrete Event Simulation (PDES) is the parallel simulation of physical systems…
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▼ Parallel Discrete Event Simulation (PDES) is the parallel simulation of physical systems that may be modeled as a series of discrete events. Such events are fine-grained and often interdependent, which poses a challenge for efficient parallel simulators. An often-employed technique for uncovering parallelism in PDES is the optimistic execution of events without regard for causality constraints. Such protocols are called optimistic protocols. Perhaps the most well-known optimistic protocol, Time Warp, aggressively executes events, rolling back to a previous state and redoing computation when a violation of causality is detected. Because violations of causality represent the primary source of inefficiency in Time Warp simulations, substantial research in the field of PDES has focused on techniques for controlling optimism and reducing rollbacks. This work extends that research to achieve optimism control by means of Dynamic Voltage and Frequency Scaling (DVFS), a power management feature found in modern microprocessors. This thesis examines the application of DVFS-based techniques to optimistic PDES simulations in order to decrease simulation execution runtimes and power consumption. Adaptive protocols for optimistic PDES simulations are reviewed, as are existing DVFS-based techniques for power management and performance enhancement. A new adaptive optimism control protocol using DVFS algorithms in TimeWarp is proposed. This protocol is implemented in C++ and tested on two shared memory machines and a 20-node Beowulf cluster. Simulation performance is measured and energy consumption is estimated for each algorithm under several balanced and imbalanced workloads. It is shown that DVFS can be used to significantly reduce performance and power consumption in optimistic PDES simulations.
Advisors/Committee Members: Wilsey, Philip.
Subjects: Computer Engineering
Keywords: DVFS; Time Warp; parallel simulation; many-core processors
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7.
Chippada, Sandeep.
Explorations of State Savings and Optimistic Fossil Collection for Parallel Simulation on Multi-core Beowulf Clusters.
Degree: MS, Engineering and Applied Science: Computer Engineering, 2012, University of Cincinnati
► Advancements in Science and Technology have increased the need for complex systems…
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▼ Advancements in Science and Technology have increased the need for complex systems that are large and powerful. Modeling and simulation serve as crucial roles in the design and development of these systems. As the size and complexity of these simulation models grow, the capacity of system memory and sequential processor performance becomes a bottleneck for the performance of these simulations. Parallelism and large scale multi-core Beowulf clusters present an option to address these memory and performance bottlenecks. However, even after parallelizing the simulation models, memory limits remain an issue to be addressed. This thesis studies several algorithms for addressing memory use for an extended version of a Parallel Discrete Event Simulator (PDES) kernel called WARPED. The extended version of WARPED incorporates threaded execution capabilities for execution on multi-core and many-core Beowulf clusters. WARPED uses the Time Warp synchronization mechanism to synchronized a distributed simulation. This thesis studies two key components for optimizing memory use in threaded WARPED, speci?cally adaptive state savings and Optimistic Fossil Collection (OFC). These methods have been previously deeveloped and studied in shared memory and single core Boewulf clusters. However, their use and effectiveness in multi-core Beowulf clusters have not been effectively studied. This thesis incorporates these optimizations into threaded WARPED and evaluates their effectiveness in multi-core Beowulf clusters. The results show that while both are reasonably effective in multi-core Beowulf clusters, the effects are less than they are in single core Beowulf clusters.
Advisors/Committee Members: Wilsey, Philip.
Subjects: Computer Engineering
Keywords: State Saving; Fossil Collection; Adaptive; Optimistic; TimeWarp; PDES
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8.
Drennan, James.
Secure Block Storage.
Degree: MS, Engineering and Applied Science: Computer Engineering, 2011, University of Cincinnati
► Data is becoming much more portable these days with thumb drives and…
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▼ Data is becoming much more portable these days with thumb drives and smart phones that can easily have gigabytes of storage. While the portability and ease of transfer of this data is beneficial, it can cause problems when it is lost or stolen. Traditionally securing data on a storage device is achieved using data encryption techniques. This can be accomplished using an encrypted filesystem such as TrueCrypt or some on-device encryption scheme such as that performed by IronKey’s secure flash memory devices. This thesis explores an alternate technique to secure data within a storage device. More precisely, a technique to authenticate each I/O (Input/Output) request issued to the storage device is explored. The device authenticates requests and responds to the request only when the authentication step succeeds. While authentication can occur with each request and is valid only for the individual request, various alternate configurations are possible where authentication is performed for various subsets of the requests. For example, authentication can be enforced only for data reads, data writes, for specific (block) address regions, and so on. For requests that fail authentication, the device may be configured with a number of response mechanisms. While these responses can be virtually anything, some notable response actions would be to: (i) act as a faulty device, (ii) respond with fake data (possibly from some onboard response prepared storage area), or (iii) destroy/erase the stored data rendering the data completely unavailable. Depending on the level of security desired, these failure modes can be temporary or permanent. Lastly, this approach can decouple the act of building an authenticable I/O request from the host and storage devices. More specifically, the I/O requests can be transmitted from the host to a third party for translation to an authenticable form. The third party could be an online server system or a nearby bluetooth device. Thus, a lost or stolen device is decoupled from the platform that builds authenticable requests thereby disabling access to the information stored in a lost device. In this thesis, the specific authenticating mechanism studied is to add a nonce to all I/O requests and then digitally sign/verify each I/O request. To demonstrate the use of this security scheme, a mechanism for attaching digital signatures to each USB request is constructed. A filter driver is added to aWindows platform to capture block requests to the USB device and route them with a nonce to a bluetooth device for computing the digital signature to attach to the request. The bluetooth device returns the signature and the filter driver packages it with the USB request for transmission to the USB device. A mass storage USB device was modified to receive and authenticate the USB packets. Unfortunately, the process of securing information in this manner is not without cost. Additional time and resources are spent signing, encrypting, and verifying the data. The time spent accomplishing these activities is affected by Bluetooth transfer rates and the microcontrollers on the devices. In particular, the implementation in this thesis impacts performance negatively due to the increase in time needed to apply and verify the security measures. In the worst case, the same actions with security measures enabled take three orders of magnitude more time. The critical performance bottleneck is in the verification step on the USB device. Thus, faster, more advanced, microcontrollers could substantially improve performance and reduce the performance impact to a more managable level.
Advisors/Committee Members: Wilsey, Philip.
Subjects: Computer Engineering
Keywords: Secure Storage; Signing requests; Encryption
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9.
Franzese, Anthony L.
Real-time Location with ZigBee Hardware.
Degree: MS, Engineering and Applied Science: Computer Engineering, 2011, University of Cincinnati
► Mechanisms for tracking assets and inventory management are widespread and well-developed. Tracking…
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▼ Mechanisms for tracking assets and inventory management are widespread and well-developed. Tracking is achieved by attaching “tags” with unique identifiers to assets and deploying “readers” throughout a facility to read the identity of the tagged assets. In general the tools and solutions for asset tracking are organized into one of two categories, namely: passive (RFID or optical barcode) solutions and real-time location systems. Passive solutions provide coarse-grained location services that record a tracked item’s movement past fixed position “reader” devices. Asset movement from location to location and into and out-of a facility are recorded. Passive systems are highly effective for inventory control and management and they are pervasive in the consumer products markets. In contrast, Real-Time Location Systems (RTLS) provide pin-point location services that can identify an asset’s location at all times. RTLS systems generally require a much larger number of expensive readers distributed throughout the monitored facility to ensure continuous communication with the tags and to allow triangulation services to precisely locate the tagged assets. Thus, existing asset tracking systems provide either inexpensive coarse-grained location services (passive solutions) or high-cost pin-point accuracy services (RTLS solutions). In many cases, the requirements for real-time asset tracking solutions do not require pin-point accuracy or continuous, second-by-second location service. For example, a solution tracking assets every 30 seconds to a coarse-grained location on the accuracy of 50-100 feet would be more than sufficient for locating wheelchairs or baggage carts in an airport, beds in a hospital, or baggage carts in a hotel. Passive solutions are ineffective because the readers can generally read only short distances (15 feet maximum) and RTLS solutions are far too expensive to be deployed throughout an airport or large scale facility such as a major hospital. This thesis examines the design of a coarse-grained asset tracking solution suitable for the needs of tracking wheelchairs in airports. The solution must be low-cost, self-organizing, and inexpensive. In this work a solution using ZigBee networking hardware is developed and analyzed. The result provides a solution where the tags are small enough to fit comfortably on wheelchairs and baggage carts and they can provide identifying broadcast signaling for at least one year using two AA batteries. The technology provides a self-organizing network where readers can be placed at reasonable distances (100-200 feet) from one another and that can provide asset tracking coverage over the largest airports in the world.
Advisors/Committee Members: Wilsey, Philip.
Subjects: Computer Engineering
Keywords: ZigBee; RTLS; Asset Tracking; RFID; Real-time Locating Systems; Sensor Network
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10.
Ganesan, Ramkumar.
Development of user interface for second generation Zinc Chip Reader device for Point-Of-Care quantification of Zinc.
Degree: MS, Engineering and Applied Science: Computer Engineering, 2012, University of Cincinnati
► The susceptibility of children to contract sepsis due to microbial invasion has…
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▼ The susceptibility of children to contract sepsis due to microbial invasion has been a cause of growing concern. Pediatric septic shock is a condition which is characterized by abnormally low levels of Zinc in the body. The augmentation of existing treatment strategies by the oral Zinc supplementation has been suggested as a therapeutic strategy to treat pediatric septic shock [1]. The clinical manifestation of Zinc deficiency and its effects on the human immune system has been extensively studied. [2, 3, 4, 5] Current methods to quantify Zinc in blood involve sending samples to specialized labs for testing which typically have a turnaround time of a few days. Hence, there is a need for a point-of care device with rapid turnaround time at the patient’s bed-side to monitor the level of Zinc in blood serum. A prototype Point-of-Care system which consists of a Lab-On-Chip sensor and a microcontroller based Zinc Chip Reader was developed by Dr. Fred R Beyette Jr. and his team in the Point-of-Care Systems Development Lab, at the University of Cincinnati[1]. The system uses a Square Wave Anodic Stripping Voltammetry (SWASV) process to quantify Zinc in a Zinc Acetate buffer solution. The results obtained using this device were found to have a significant margin of error due to the use of a 10-bit analog-to-digital converter which provides inadequate digitization for the measurement of current by the instrument. Additionally, the device is cumbersome to use in a clinical setting due to its lack of user interface that would enable the input of key parameters for the SWASV process. Finally, the device lacks a visual display necessary to communicate with the user during the SWASV process. This thesis is focused on the development and implementation of the second generation Zinc Chip Reader device with a convenient user interface and reduced digitization error. The digitization error of the system is improved by implementing a 12 bit analog-to-digital converter to digitize the signals during data acquisition. The user interface is improved by the use of a LCD display module and a 4 X 4 keypad matrix which is built with SPST tactile switches. The reliability of the system has also been improved by the addition of filters at the power rails and at the signal output. This thesis reports the design and functional demonstration of the prototype second generation Zinc Chip Reader device.
Advisors/Committee Members: Beyette, Fred.
Subjects: Electrical Engineering
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11.
Gujarathi, Neha.
A Performance Based Comparative Study of Different APIs Used for Reading and Writing XML Files.
Degree: MS, Engineering and Applied Science: Computer Engineering, 2012, University of Cincinnati
► Recently, XML (eXtensible Markup Language) files have become of great importance in…
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▼ Recently, XML (eXtensible Markup Language) files have become of great importance in business enterprises. Information in the XML files can be easily shared across the web. Thus, extracting data from XML documents and creating XML documents become important topics of discussion. There are many APIs (Application Program Interfaces) available which can perform these operations. For beginners in XML processing, selecting an API for a specific project is a difficult task. In this thesis we compare various APIs that are capable of extracting data and / or creating XML files. The comparison is done based on the performance time for different types of inputs which form different cases. The codes for all the different cases are implemented. Two different systems, one with Windows 7 OS and another with Mac OS are used to perform all the experiments. Using the results found we propose a suitable API for a given condition. In addition to the performance, programming ease for these APIs is taken into consideration as another aspect for comparison. To compare the programming ease, aspects such as number of lines of code, complexity of the code and complexity of understanding the coding for the particular API are considered. Thus, we are also able to suggest an appropriate API based on programming ease.
Advisors/Committee Members: Purdy, Carla.
Subjects: Computer Engineering
Keywords: XML; Parsers; API; Performance based comparison of XML processing API; SAX, StAX; DOM, JDOM, DOM4J
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12.
Han, Qiang.
An Error-Tolerant Dynamic Voltage Scaling Method for Low-Power Pipeline Circuit Design.
Degree: MS, Engineering and Applied Science: Computer Engineering, 2012, University of Cincinnati
► In recent years, many innovative researches have been conducted on dynamic voltage…
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▼ In recent years, many innovative researches have been conducted on dynamic voltage scaling (DVS), such as Razor [1]. This thesis presents an error-tolerant DVS design that can enhance the reliability and reduce the power consumption of a pipeline circuit simultaneously. Based on delay distributions of all pipeline stages, an efficient voltage island partitioning method is developed to cluster all pipeline stages into several voltage islands. By assigning the best voltages to stages, the DVS design can enable the pipeline stages to work at an optimal energy consumption with least performance penalty. Experimental results obtained by HSPICE and Matlab simulations demonstrate the feasibility of this method.
Advisors/Committee Members: Jone, Wen Ben.
Subjects: Computer Engineering
Keywords: VLSI; Low power design; Dynamic voltage scaling; Pipeline circuit
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13.
Jayaram, Indira.
Adding non-traditional constraints to the embedded systems design process.
Degree: MS, Engineering and Applied Science: Computer Engineering, 2011, University of Cincinnati
► Embedded systems are ubiquitous and have a large number of applications. The…
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▼ Embedded systems are ubiquitous and have a large number of applications. The requirements for embedded systems are not restricted to functionality but also include a lot of non-functional properties such as cost, reliability, safety, ease of use etc. This makes developing a standard design methodology for embedded systems challenging. In this thesis, we are attempting to include the non-traditional, non-functional constraints of embedded systems in the design process by weighting them in the order of their importance. We propose developing UML models for a system and annotating them with the non-functional constraints by using standard profile extensions and weighted constraint charts. We demonstrate the application of this design technique by developing a few example systems. One of the systems is implemented on Altera UP3 platform and demonstrates how the design technique leads us to choose the implementation that satisfies all the requirements, including the ones that are non-functional.
Advisors/Committee Members: Purdy,, Carla.
Subjects: Computer Engineering
Keywords: Embedded systems; UML; MARTE
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14.
Joshi, Yogesh.
Hardware encryption of AES algorithm on Android platform.
Degree: MS, Engineering and Applied Science: Computer Engineering, 2012, University of Cincinnati
► Mobile devices have revolutionized the world more than any other technology could…
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▼ Mobile devices have revolutionized the world more than any other technology could have ever done. They have become an all purpose device performing numerous functions, thus eliminating the need of carrying multiple devices. In today’s world mobile phones are seen more as a necessity than a luxury. It has changed the way people communicate with one another, allowing almost everyone to speak to anyone else no matter where they are. In 1999, only 8 percent of the world population had mobile phone subscriptions. By 2007, this figure increased to 49 percent and today 77 percent of the world’s population has mobile phone subscription, out of which 10 percent are Smartphone users. Smartphone is the category of mobile phones which has higher processing power and third party application support. In addition to the basic phone functions, Smartphone can be used to surf the web, listen to music, capture images, shoot videos and even play games. Gone are the days when it was necessary to carry cash and check for money transaction. In recent years this medium has been replaced by credit card, which will eventually be replaced by mobile transactions. The market of Smartphone has evolved over a period of time and data security has now become a major concern. The use of Smartphone for online transactions has made it necessary to provide greater security to these handheld devices. As of now, secure data exchange on these devices is dependent on software implementation of cryptographic algorithms. To make the process robust, it becomes necessary to add this stage of security at hardware level itself. This research proposes a space and power efficient hardware model of 128-bit Advanced Encryption Standard (AES), which can be distributed as secure digital (SD) card and incorporate plug and play capability. This implementation fits in low cost Spartan 3 XCS1500 Field Programmable Gate Array (FPGA). It operates at 1020 MHz or 710 MHz and produces a throughput of 1099 and 710.9 Mbps. At 1020MHz it consumes 8.5nJ energy per operation cycle and at 710 MHz it consumes 10.5nJ of energy per cycle.
Advisors/Committee Members: Wilsey, Philip.
Subjects: Computer Engineering
Keywords: Hardware Encryption; AES-128 bit; Android platform; FPGA Encryption; Smartphone Security; Secure Mobile Transactions
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15.
Kamepalli, Phanindra.
User Interface and Modified Testbench to Support Comprehensive Analysis of Protein Structural Alignment Tools.
Degree: MS, Engineering and Applied Science: Computer Engineering, 2011, University of Cincinnati
► Protein structural alignment is the study of equivalences between the structures of…
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▼ Protein structural alignment is the study of equivalences between the structures of proteins. In order to study structural alignment various tools are developed. Each tool uses different algorithms and methods to compare the structures. It is essential to find out which tool yields better results under different test cases so that more efficient tools can be developed in the future. To test the tools a comprehensive testbench data set is necessary. Our work is aimed at studying available structural alignment tools, extending previously developed testbench data set, and developing a user interface to support the modified testbench and comprehensive analysis of protein structural alignment tools.In our research we have studied all 18 protein structural alignment tools available and have done a comprehensive analysis of their performance by using our modified testbench data set. The protein pairs in the testbench data set are divided into 11 categories for comprehensive analysis of the structural alignment tools. Based on our results we ranked the tools according to their performance in each category. The overall rank is also given. Our testbench data set is configured such that, in future, if a new tool is developed and is tested on our data set, we can easily rank the tool’s performance.
Advisors/Committee Members: Purdy, C, Carla.
Subjects: Bioinformatics
Keywords: Protein structural alignment tools; Testbench
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16.
Kedalagudde, Meghashree Dattatri.
Adding extensions to UML dynamic models for better embedded system design.
Degree: MS, Engineering and Applied Science: Computer Engineering, 2012, University of Cincinnati
► An important facet of embedded system design today is hardware software co-design.…
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▼ An important facet of embedded system design today is hardware software co-design. And another important trend is that the Unified Modeling Language (UML) is increasingly being considered for modeling embedded systems due to the number of advantages this language offers. But there are a few drawbacks with UML that act as a hindrance for efficient embedded system design. Overcoming these drawbacks is a challenging task. In this work, we attempt to develop a complete specification of the system under design at the design phase of the process using UML that could directly be used to implement the system efficiently. In this thesis, this is achieved by proposing a few new extensions to the sequence and state chart diagrams in UML that define the dynamic behavior of the system under consideration. The extensions are demonstrated and the highlights and usefulness of the extensions explained through a few example designs.
Advisors/Committee Members: Purdy, Carla.
Subjects: Computer Engineering
Keywords: UML; design; dynamic models
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17.
King, Randall.
WARPED Redesigned: An API and Implementation for Discrete Event Simulation Analysis and Application Development.
Degree: MS, Engineering and Applied Science: Computer Engineering, 2011, University of Cincinnati
► In 1995, researchers at the University of Cincinnati released WARPED as a…
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▼ In 1995, researchers at the University of Cincinnati released WARPED as a publically available discrete event simulation kernel. The goal of the project was to provide a system for research and analysis of the Time Warp distributed simulation synchronization protocol. WARPED was to be efficient, maintainable, flexible, configurable, and portable. It was written in C++ and used the Message Passing Interface (MPI) standard to accommodate as many parallel platforms as possible. As the software implementation was expanded with additional capabilities and optimizations, several problems with the original design became apparent. The primary problem was that the configuration of various Time Warp optimizations could only be made at compile time. As simulations increased in size and complexity, this compile time became a significant burden. Another problem, related to the first, was that WARPED could not be used and distributed as a shared library due to the compile time configuration requirement. This thesis discusses the design and implementation of the Time Warp mechanism in a new version of WARPED, now called the WARPED v2.x series (the initial series is now called the WARPED v1.x series). The primary goal of WARPED v2.x is to provide run time configuration of the system. The goals of the previous version carry over to the new version. Several simulation models are also included in the initial release of the WARPED v2.0 distribution for use in analyzing the system. In this initial version of WARPED v2.x, the system includes sequential and parallel simulation kernels that can be configured at run time for use with any of the simulation models compliant with the WARPED API. The parallel simulation kernel uses the Time Warp distributed synchronization mechanism and includes several Time Warp optimizations, including: various cancellation strategies, fossil collection algorithms, GVT estimation algorithms, state saving algorithms, event list structures, scheduling algorithms, and support for multiple communication protocols (all organized to support run time configuration/selection). This thesis presents the issues and difficulties of implementing the optimizations along with the solutions used. The optimizations are analyzed using performance data and system profiling. With the available simulations and extensible design, WARPED v2.0 can be used to explore new optimizations for the Time Warp mechanism.
Advisors/Committee Members: Wilsey, Philip.
Subjects: Computer Engineering
Keywords: Parallel Discrete Event Simulation; Time Warp; Distributed Simulation
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18.
Kolla, Purushotham Pothu Raju.
Parallel Garbage Collection in Solid State Drives.
Degree: MS, Engineering and Applied Science: Computer Engineering, 2012, University of Cincinnati
► Flash memories are making their way into both desktop and server environments.…
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▼ Flash memories are making their way into both desktop and server environments. Over the years, the major limitation to the wide-adoption of flash memories has been their cost. However, with the advancements in the semiconductor industry, the price per gigabyte (GB) gap between the conventional disk drives and flash memories is getting closer. As such, flash memories can replace disks, where disk utilization is less and extra spindles are added just to increase performance. Though they ventured into the storage architecture as cache and as a hybrid counterpart with Hard Disk Drives (HDD), slowly they are expected to replace the disk drives in servers and super computers [1]. The other major drawback with flash memory is its inability to sustain unlimited erase cycles, which directly limits their lifetime [2]. In order to improve reliability, it is proposed to create redundancy [3]. Creating a Redundant Array of Independent Disks (RAID) is a conventional way of providing redundancy in hard disk drives (HDD) [4]. The same idea is adopted in Solid State Drives (SSD). In addition to the conventional RAID techniques that are implemented at the device level (external RAID), redundancy can be created in an SSD at a much lower level (internal RAID) [3]. The scope of this work is limited to internal RAID. This work uses i-RAID [3]; an architecture and simulator for internal RAID as background and proposes two improvements. The first contribution is to improve the dynamic stripe formation using access patterns. Another enhancement is to utilize the idle domains when i-RAID is not active by invoking parallel instances of garbage collection. This thesis describes how these methods can affect the performance of the device and explains how the internal parallelization of an SSD can be better exploited. Both the methods are evaluated individually and the findings are presented. Though both the methods have a great potential to improve the performance of the device, the earlier work (on which the current work is based) is done in such a way that exploiting access patterns during stripe formation could not provide much improvement.
Advisors/Committee Members: Hu, Yiming.
Subjects: Computer Engineering
Keywords: Solid State Drives; SSD; Garbage Collection; RAID; Flash Memory; Access Patterns
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19.
Korukonda, Harika.
A Generic Agent Based Modeling Tool for Simulating Bio-Molecular Systems.
Degree: MS, Engineering and Applied Science: Computer Engineering, 2011, University of Cincinnati
► Agent based modeling (ABM) is a type of computational modeling system which…
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▼ Agent based modeling (ABM) is a type of computational modeling system which concentrates on interactions between the components of a model. It is thus based on a bottom-up paradigm. In systems biology, Agent based modeling is an emerging powerful tool. The main reason for its success lies in the fact that it can easily take into account the spatial dynamics and geometries of systems. Other modeling techniques fail to model the spatial interactions between the components. This research work aims at providing GenericSystem, an easy-to-use tool to simulate bio-molecular systems in MASON, a widely used ABM implementation. A basic GenericSystem is modeled in MASON. This system contains all the basic classes and functions that can best describe a typical bio-molecular system. All the classes and functions are based on usage of JAVA for programming. This tool is designed to be very easy to use and understand. It has well defined functions which can be readily customized and thus reduces the development time of the model. The model can be viewed by the rich GUI offered by MASON. Five systems, k bioluminescence in Vibrio fischeri bacteria, skin regulatory system, Phage Lambda system, epithelial cells growth cycle and Wnt signaling pathway have been successfully implemented using the GenericSystem tool. Various parameters for the systems have been changed and simulations run for various conditions. The simulations and previous work are compared and conlusions are drawn. Scope of future work has been provided.
Advisors/Committee Members: Purdy, Carla.
Subjects: Computer Engineering
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20.
Kothottil, Dinek.
Markov-based Predictive Models For Estimation of Degradation Rates of Bridges in the State of Ohio.
Degree: MS, Engineering and Applied Science: Computer Engineering, 2010, University of Cincinnati
► Ohio Department of Transportation maintains a bridge management system which contains historical…
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▼ Ohio Department of Transportation maintains a bridge management system which contains historical inspection and inventory data for about 50,000 bridges in Ohio for the last 26 years. Statistical analysis of the data in BMS can provide insights to the degradation rate of bridges in different parts of the state of Ohio and aid ODOT in their planning and budget allocation. ODOT utilizes an excel spreadsheet namely the ODOT Forecasting Spreadsheet to record its forecasted maintenance and budgeting activity for the coming years. The forecasted maintenance and budget allocation is based on a constant degradation rate for each of the four organizational performance indexes namely General Appraisal, Deck Floor Condition, Deck Wearing Surface and Protective Coating System. Data from bridge management system made available in the form of excel sheets were extracted, cleansed and loaded to MySql database. Data modeling techniques like Markov Model and Auto regressive models are applied to the BMS data for OPI forecasting and trending. An analysis of the BMS data has shown that the degradation rates of bridges in Ohio are seldom a constant. Degradation rate depends mainly on the maintenance and policy changes in ODOT. Two approaches namely fixed STM approach and a moving window of STM approach is described to capture the degradation rate of bridges in Ohio. The degradation rates thus obtained can be utilized in the forecasting spreadsheet for accurate planning and budget allocation. Analysis of the degradation rate of bridges in each district is also done and this helps provide the performance of each district as against the expected performance in terms of maintenance and funds allocated to the districts by the ODOT.
Advisors/Committee Members: Helmicki, Arthur.
Subjects: Computer science
Keywords: degradation rate; markov models; odot
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21.
Kuchi, Chandra K.
Implementing Space and Time Non-linearity in Virtual Worlds.
Degree: MS, Engineering and Applied Science: Computer Engineering, 2011, University of Cincinnati
► 3D virtual worlds provide rich environments for collaborative work and social networking.…
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▼ 3D virtual worlds provide rich environments for collaborative work and social networking. The design of these spaces is has largely been designed and limited by the classical linear time and space properties that we find in our own physical world. In some cases, some non-physical ca- pabilities like teleportation are provided, but in general, most of the limits that we experience physically such as time linearity, gravity, orientation, and single location, are also experienced in these computer-based virtual worlds. This thesis, explores relaxing the linear constraints of time and space in a 3D virtual world. In particular, the thesis explore extensions that have been made to a Second Life (a 3D virtual world) viewer to bend the time and space barriers from conventional limits. The modifications are inspired by the concepts of picture-in-picture and DVR in modern television viewing systems. These extensions are called: multi-view which allows the viewer to monitor multiple locations in the virtual world (allowing a user to observe and switch quickly be- tween multiple virtual locations), and pause-view which allows the user to pause and then continue (possibly in faster than real-time) a meeting stream (much like the pausing of a TV program made possible by digital video recorders). Providing faster than real-time playback allows the viewer to catch up (from a pause or late meeting arrival) so that they can, for example, participate in a closing Q and A session. The technical and functional modifications, benefits with emphasis on architectural details are described. Evaluation results of these new User Interface design are presented. Excit- ing possibilities for second life community due to the introduction of these new dimensions are discussed.
Advisors/Committee Members: Wilsey, Philip.
Subjects: Computer Engineering
Keywords: Virtual Words; Multitasking; Second Life; Multi-View; Pause-View; CSCW
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22.
Miller, Ryan J.
Optimistic Parallel Discrete Event Simulation on a Beowulf Cluster of Multi-core Machines.
Degree: MS, Engineering and Applied Science: Computer Engineering, 2010, University of Cincinnati
► The trend towards multi-core and many-core CPUs is forever changing the composition…
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▼ The trend towards multi-core and many-core CPUs is forever changing the composition of the Beowulf cluster. The modern Beowulf cluster is now a heterogeneous cluster of single core, multi-core, and even many-core processors. Distributed discrete event simulations which are common tasks for such clusters are in the position now to take full advantage of this new environment by moving away from the single heavy-weight processes and converting to a many thread processes capable of fully utilizing a multi-core CPU. This research focuses on expanding the current warped discrete event simulation kernel to take full advantage of these heterogeneous Beowulf clusters. Through this research, multiple lock-free data structures, as well as shared memory discrete event simulation algorithms were implemented and analyzed. In the analysis of the first Threaded Warped implementation, named ThreadedWarped, several key weaknesses are defined which caused an actual worsening of the performance versus that of the single heavy-weight process implementation. With solutions to some of these weaknesses given, ThreadedWarped makes for a solid foundation on which to continue research in this area of optimistic distributed shared memory parallel discrete event simulation.
Advisors/Committee Members: Wilsey, Philip.
Subjects: Computer science
Keywords: discrete event simulation; warped; parallel; threads; lock free
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23.
Nafziger, Jonathan W.
A Novel Cache Migration Scheme in Network-on-Chip Devices.
Degree: MS, Engineering and Applied Science: Computer Engineering, 2010, University of Cincinnati
► Future Network-on-Chip (NoC) designs no longer map single cores to each cache…
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▼ Future Network-on-Chip (NoC) designs no longer map single cores to each cache slice but rather multiple cores in layouts known as hybrid architectures. Additional proposals have suggested creating reconfigurable hybrid architectures where the OS can revise core-to-cache mappings as required. However, these designs will still be measured by their ability to reduce the average L2 cache delay. Denser core placements with varying core mappings require cache policies with intelligent data placement schemes otherwise there will be no gain to overall system performance as a result of the networked architecture. Solutions such as OS-directed page placement can reduce some of this delay by placing pages in caches local to the initial requestor. However, due to the page-level allocation granularity compared to line-level data accesses, this policy can still result in shared data existing in remote locations during highly parallelized applications. The most effective network delay reduction alternative is line-level data migration. Data migration policies are designed to take advantage of data temporal locality by assuming data recently used by a processor will be used again in the future. Several variations of migration policies have been proposed to address this demand. However, the physical costs, high computation demands and poor scalability of these methods have reduced their effectiveness in future layouts with hundreds of cores. Additionally, many proposals fail to consider migrating data to a centralized location with even latencies for multiple active cores instead they reduce latency for a single core at the expense of all others. This best average placement is also known as the nearest-neighbor search or the “Two-Dimensional Post Office Problem”. The proposed Directional Migration solution attempts to solve these problems by providing an autonomous, line-level migration that is responsive to multiple cores with varying access patterns. This design maintains two usage sensors in the form of physical counters on a per-cache-line basis. Migrations traverse only a single network hop to reduce in-transit delays, providing finely-tuned movement and responsiveness to changes in future access patterns. This migration policy is further enhanced by the addition of the Active Neighbor Migration policy. This method is a unique implementation which proposes consideration of data spatial locality. Here each triggered migration causes analysis of logically neighboring lines for potential early migrators. The Directional Migration solution with the Active Neighbor Migration policy provides a solution to the nearest-neighbor search with a constant physical cost in relation to the number of cores and size of the network while maintaining a linear physical cost in relation to the size of the cache. This is of enormous importance as the size of networks and volume of cores on a single device grow. The physical cost is also independent of the number of shared or migratory lines as the volume of such continues to grow exponentially due to highly parallelized applications. Finally, this solution provides an adaptive response to changes in network layout and core density as necessitated by any NoC architectures.
Advisors/Committee Members: Vemuri, Ranganadha.
Subjects: Electrical engineering
Keywords: Network-on-chip; NoC; Cache; Data Migration; Spatial Locality; Temporal Locality
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24.
Panda, Amayika.
A Novel Configurable Benchmarking System for Multi-core Architectures.
Degree: MS, Engineering and Applied Science: Computer Engineering, 2011, University of Cincinnati
► Multi-core architectures have been an important area of research in recent years.…
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▼ Multi-core architectures have been an important area of research in recent years. This has been driven by the constant need to improve the performance of computing systems. We have witnessed a shift in technology from the pure bus based architectures, to the more scalable Network on Chip (NoC) architectures. There have also been proposals for a hybrid approach, that derives concepts from both the bus based and NoC architectures. These systems are designed to exploit the benefits of parallelism and cope with an increased amount of multi-tasking. As these architectures continue to evolve, the need for a suitable benchmarking tool to measure, compare and evaluate them becomes paramount. Many benchmark suites that are widely used in industry and academia are algorithm centric and usually favor one type of system over the other. They have not evolved much from their single core counterparts. Furthermore, micro-benchmarks emphasize on evaluating only a few metrics making it hard to evaluate a system in its completeness. Often, the system designers have little control over the capabilities of the benchmark. They use different benchmarks in order to evaluate systems against different metrics. In this work we propose a new benchmarking methodology that provides more control to the system designer. The benchmarks generated by our tool are configurable by a set of user defined parameters. The configurations can easily be altered to represent different real world application scenarios. They can also be reused and published as an open benchmarking standard. We also propose a second computational benchmark tool that can be used to design parallel computational workloads, with adequate interdependencies in a customizable environment.
Advisors/Committee Members: Vemuri, Ranganadha.
Subjects: Computer Engineering
Keywords: benchmark; multi-core; architecture; configurable; benchmarking; multiprocessor
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25.
Pattabiraman, Aishwariya.
Heterogeneous Cache Architecture in Network-on-Chips.
Degree: MS, Engineering and Applied Science: Computer Engineering, 2011, University of Cincinnati
► Current trends in multicore research suggest that hundreds of cores will be…
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▼ Current trends in multicore research suggest that hundreds of cores will be integrated on a single chip in the future for high performance. Increasing the number of cores increases execution speed. However, performance of the system also depends on the cache access speed. Several ideas have been suggested for the cache management in multicore systems. The wire delay in large unified on-chip caches and the need for higher bandwidth have made banked caches connected by two dimensional switched network the choice for the last level cache organization. In the NoC structure accessing nearby cache banks is faster than accessing remote banks. Hence it is called Non-Uniform Cache Architecture (NUCA). In NUCA since the cache access latency depends on the cache bank that is accessed, we need to find efficient methods to place data in the cache banks close to the accessing core. Data migration methods migrate data lines to the cache banks close to the accessing cores during their runtime. However, good initial data placement methods are necessary to achieve low cache access times. They can be used along with the existing data migration schemes. Many software techniques like locality aware data placement and management of cache capacity allocation between processes have been suggested in literature. However, they fail to take advantage of the physical distribution of last level cache among the tiles. Much less has been done to combine both hardware and software techniques to reduce the cache access latency. In this thesis, we have shown that equal distribution of the cache among the tiles in NoCs may not be the optimal cache distribution for all workloads. Therefore we propose static heterogeneous cache architecture for multi-programmed workloads. The heterogeneity and the appropriate scheduling by the OS will help to reduce network hops by placing more cache blocks close to the cores executing data intensive process. Furthermore, we also propose dynamic heterogeneous cache architecture for multi-threaded workloads. In multi-threaded workloads, data lines are shared by a number of cores. Initial placement of the shared data lines close to one of the accessing cores may lead to higher access times for other cores. Also, the optimal cache configuration varies depending on how the data is shared between processes in each workload. These aspects are considered in this work to formulate the page coloring and cache allocation as a placement problem. A constructive heuristic has been presented which gives the optimal cache configuration and page coloring for each workload. Both static and dynamic cache configuration exploit the underlying architecture and existing OS level software policies to provide lower cache access latencies for future CMPs. Finally, both of these methods are scalable and suit future workloads effectively.
Advisors/Committee Members: Vemuri, Ranganadha.
Subjects: Computer Engineering
Keywords: Cache Architectures; NoC; Heterogeneous
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26.
Rakurthi, Aparna.
Development of an Optical Heart Rate Monitor using a Microchip PIC24-microcontroller based development board.
Degree: MS, Engineering and Applied Science: Computer Engineering, 2012, University of Cincinnati
► The primary goal of this thesis is to develop a prototype device…
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▼ The primary goal of this thesis is to develop a prototype device that can be used to demonstrate some key and fundamental concepts related to the disciplines of computer and electrical engineering to freshman engineering students. This objective is achieved through the development of a heart rate monitor that primarily consists of a sensor module for heart beat detection and a Microchip PIC-microcontroller based development board for heart rate calculation. The central element of the sensor module is an optical detection system that consists of a light-emitting diode and photodiode setup to detect heart beat from a measurement site with strong pulse like a fingertip. The obtained heart beat signal is then passed through multiple amplification and filtering stages to obtain a clean and strong heart beat signal. Using this optical sensor module implemented on a printed circuit board (PCB) we can demonstrate several concepts related to electrical engineering such as: basic electronics, semiconductor devices, analog circuit design, optical electronics, PCB design, etc. The voltage signal obtained from the sensor module is sent to a Microchip Explorer 16 development board for further signal processing and heart rate calculation. The development board contains a 16-bit PIC microcontroller with a built in 10-bit analog-to-digital converter that is used to digitize the analog voltage signal and calculate heart rate as beats per minute using a heart rate calculation algorithm. The calculated heart rate is finally displayed on an alphanumeric liquid-crystal display display that is included on the development board. This module of the prototype heart rate monitoring system is designed to be interactive and provide user-control to the heart rate calculation process while demonstrating some concepts related to computer engineering such as: microcontrollers, embedded systems, software development, hardware/software co-design, etc. The heart rate monitor developed in this research work has thus been designed to present a prototype device that can be used to demonstrate several key concepts related to computer and electrical engineering and this thesis document contains design and implementation details related to the development of this device.
Advisors/Committee Members: Beyette, Fred.
Subjects: Computer Engineering
Keywords: Optical Heart Rate Monitor; PIC24; Microchip development board; Microcontroller
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27.
Ramakrishnan, Lakshmi Narasimhan.
SDMLp - Secure Differential Multiplexer Logic : Logic Design for DPA-Resistant Cryptographic Circuits.
Degree: MS, Engineering and Applied Science: Computer Engineering, 2011, University of Cincinnati
► Hardware Security is a key issue with the emergence and proliferation of…
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▼ Hardware Security is a key issue with the emergence and proliferation of embedded systems. Many embedded systems like smart cards, RF-id tags, mobile phones and PDAs run cryptographic algorithms running on dedicated cryptographic ICs to perform operations like secure identification, authentication and communication. Even though cryptographic algorithms are mathematically strong and secure, the underlying hardware (CMOS) implementations may reveal the secret key of the device by exhibiting data or operation dependent power consumption. Attack methodologies that use information like power consumption, timing information and electromagnetic radiation of the Cryptographic IC to find the secret key of the device are called Side Channel Attacks. Differential Power Analysis (DPA) is a category of Side Channel Attack that uses differences in power consumed for different input vectors along with statistical analysis to reveal the secret key in the device. DPA attacks are possible due to the data dependent power consumption of the CMOS circuits. Several algorithmic, circuit and logic level countermeasures have been proposed to resist DPA attacks. Unfortunately many of these techniques are either ineffective or end up having a huge overhead in other design metrics like area, power and speed. The objective of DPA resistance is to remove data dependence from power consumed. Recently, many circuit design techniques based on Dynamic and Differential Logic, which allows for matching power profiles regardless of input, have been proposed. In this thesis, we present a universal cell called SDMLp (Secure Differential Multiplexer Logic), based on differential pass transistor logic, to mitigate DPA attacks. A single two input SDMLp cell can be configured to perform all possible 16 two input logical operations. Employing SDMLp cells in circuit design increases the DPA resistance of the circuit by exhibiting 10 to 100 fold reduction in instantaneous power variance compared to existing DDL based secure logic styles and nearly 1000 fold compared to SCMOS designs. Apart from improvement in instantaneous current variation, we also show nearly 60% to 70% reduction in power consumption and nearly 45% to 50% reduction in area compared to existing DDL based secure logic styles.
Advisors/Committee Members: Vemuri, Ranganadha.
Subjects: Computer Engineering
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28.
Ravi, Ajaay.
Run-Time Active Leakage Control Mechanism based on a Light Threshold Voltage Hopping Technique (LITHE).
Degree: MS, Engineering and Applied Science: Computer Engineering, 2011, University of Cincinnati
► Leakage aware designs are an indispensable part of the design and manufacturing…
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▼ Leakage aware designs are an indispensable part of the design and manufacturing process in today’s deep sub-micron technologies. Technology scaling continues to be a constant factor in CMOS designs, with the feature sizes of devices manufactured being scaled down below 28nm. Starting from the 45nm technology, it has been shown that the leakage power consumption in a circuit catches up with the dynamic power consumption and continuing this trend, it has been projected that for future technologies, the leakage power consumption will even dominate the dynamic power consumption. This increasing leakage power consumption in the deep sub-micron CMOS technologies has manifested the need for more aggressive control mechanisms. The leakage control mechanisms in use today can be widely categorized into 2 categories namely, Design-Time control mechanisms and Run-Time control mechanisms. As the names suggest, Design-Time control mechanisms are incorporated into the circuit during the design phase and are not capable of dynamic control. This limits the extent of effectiveness in the leakage power reduction capability of this technique. Alternatively, Run-Time leakage control mechanisms monitor the circuit and dynamically flip it into a low power mode of working, depending upon the circuit’s workload. These techniques yield a significant power saving and a significant amount of research in low power designs today, is directed towards this technique. The research presented by means of this thesis, is based upon a prominent run-time control mechanism known as Reverse Body Biasing. The workload of any circuit can be defined under 2 broad classifications, viz. Active mode and Standby mode. There are many robust leakage power reducing techniques that are in use today to tackle the issue during the standby mode of a circuit. It is the active mode that presents an interesting view to the problem as a whole. Scrutinizing the workload of a circuit in its active mode of working showcases that there are copious opportunities of slackness that a designer can take advantage of and utilize to construct a better leakage aware design. This is classified as Run-Time Active leakage control (RALC). Key issues to using RALC are the optimum granularity level on which it can be applied and deciding on an efficient leakage reduction mechanism to be used with it. These issues are addressed by the technique presented as the central idea of this research, known as LITHE (Light Threshold Voltage (VTH) Hopping Technique). The idea behind LITHE is based off of a popular technique known as Threshold Voltage hopping and this is achieved by means of Adaptive Substrate Biasing. Together, this forms the core of this research. This research aims to convincingly address all the issues of the RALC as a viable solution to designing robust leakage aware designs. Aggressive exploitation of idleness during the active mode working of a circuit, fused together with the idea of LITHE, is the solution proposed towards tackling leakage power issues in deep sub-micron technologies, by means of this research. Extensive experimentation has been performed on benchmark circuits to support and verify its accuracy.
Advisors/Committee Members: Vemuri, Ranganadha.
Subjects: Computer Engineering
Keywords: Leakage Power Reduction; Run-Time Active Leakage Control; Threshold Voltage Hopping; Substrate Biasing; LITHE; Steady state leakage current reduction
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29.
Seethakkagari, Swathi M.S.
Identifying Interesting Posts on Social Media Sites.
Degree: MS, Engineering and Applied Science: Computer Engineering, 2012, University of Cincinnati
► This thesis work considers the classification of messages posted on social networking…
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▼ This thesis work considers the classification of messages posted on social networking sites as a step towards identifying interesting/uninteresting messages. As first approximation, a message is represented by a few attributes including the message length (number of words), posting frequency (time difference between consecutive messages) for the same sender, comments and likes (received for the previous posts). Keywords in the posts can also be considered as a parameter. A classifier, trained according to the user's perception of whether a message is interesting or not, is used to label each message. In this thesis we consider the two different classifiers, k- Nearest Neighbor Classifier and Naive Bayes Classifier. Facebook is considered for illustration purposes.
Advisors/Committee Members: Ralescu, Anca.
Subjects: Computer Science
Keywords: Social networks; k-nearest neighbors; Naive Bayes Classi- fication; Confusion Matrix
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30.
Shary, Stephen.
Java Simulator of Qubits and Quantum-Mechanical Gates Using the Bloch Sphere Representation.
Degree: MS, Engineering and Applied Science: Computer Engineering, 2011, University of Cincinnati
► One of the most promising paradigms for the development of novel high-speed…
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▼ One of the most promising paradigms for the development of novel high-speed and energy efficient devices is spin electronics or spintronics. It is based on the simultaneous manipulation of the electron spin and large degrees of freedom. It offers the possibility of developing electronic devices based on the control of the electron spin. The spin polarization of a single electron can exist in a coherent superposition of two orthogonal spin polarizations (i.e. mutually anti-parallel spin orientations) for a relatively long time without losing the phase coherence. The charge degree of freedom, on the other hand, loses phase coherence much faster. Therefore spin has become the preferred vehicle to host a quantum bit (or "qubit") which is a coherent superposition of two orthogonal states representing classical logic states of 0 and 1. The potential application of spin manipulation to a scalable quantum logic processor has led to the field of quantum computing. To date, several physical quantum computers have been proposed which all require appropriate mechanisms to create, manipulate and measure individual spins. Each operation can be mapped to the action of a quantum-mechanical system acting on the spin state of the electron also known as the qubit state. The Bloch sphere is a useful tool to represent the actions of various quantum-mechanical operators on a spinor because it provides a visual representation of the qubit state evolution. Most importantly, it provides a link between the rather abstract concept of a spinor and the more intuitive way (although not rigorous) of thinking of the spinor of the electrons being associated with an intrinsic magnetic moment. In this thesis, a simulation software is built to provide a visual representation of a quantum state or qubit based on the Bloch sphere representation. This software uses the Java language and libraries to provide a multi-platform simulator that can be quickly distributed and viewed using the Java web-start technology. This simulator shows the different qubit states, their representation in both the two dimensional complex plan along with the bra-ket representation. It provides the ability to visualize simple basic operators representing the action of quantum gates. It allows the user to enter simple operations which can be represented by the action of 2x2 matrices. It also features some more complex functionality important in spintronics including the Larmor precession and the spin flip process under the combined action of a constant and rotating magnetic field as described by the Rabi formula.
Advisors/Committee Members: Cahay, Marc.
Subjects: Computer Engineering
Keywords: Quantum Computation; Bloch Sphere; Spintronics
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