Department: Engineering : Computer Science and Engineering ![[clear]](close-x.png "Remove this limiter")
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1.
AGARWAL, ANURADHA.
ALGORITHMS FOR LAYOUT-AWARE AND PERFORMANCE MODEL DRIVEN SYNTHESIS OF ANALOG CIRCUITS.
Degree: PhD, Engineering : Computer Science and Engineering, 2005, University of Cincinnati
► With the ever increasing complexity of integrated circuits and constantly shrinking device…
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▼ With the ever increasing complexity of integrated circuits and constantly shrinking device sizes, the need to develop entire dystems on chip (SoC) has received a significant momentum. With this need,comes the responsibility of bringing about mature computer-aided design (CAD) techniques to handle the complexity of designing such systems. Although mature commercial techniques exist for designing the digital components in a system, design automation for the irreplaceable analog and radio-frequency (RF) circuits in a system remains incipient. Circuit sizing is one of the most important and challenging constituents of any analog design process. Given a set of high-level specifications and a circuit topology, sizing aims to determine the device dimensions and biasing information in order to meet the desired specifications. In this dissertation, we address two major problems ailing the sizing process. One of the most important challenges in analog synthesis is to design a circuit which meets the input specifications at the post-layout stage. The other problem we seek to address in this dissertation is the enormous time spent in sizing due to the overhead of running thousands of simulations for performance estimation. Analog and RF circuits are extremely sensitive to layout parasitics. This extreme dependence of the behavior of analog circuits, on layout-induced parasitics, is responsible for several silicon runs before a functional chip can be designed. We propose two techniques to introduce layout awareness during circuit sizing. The first approach is based on developing fast and accurate models of the layout parasitics. The parasitic capacitance models are used inside a circuit sizing framework to estimate the layout parasitics and account for them in the performance evaluation process. This approach relies on procedural layout generators (PLGs) for developing the parasitic models. The second approach proposed for layout-aware design draws a similarity between layout parasitics and process variables in a yield optimization problem. A two-step approach is proposed for identifying the worst case parasitic corners and for sizing in presence of these parasitics. A parasitic robust design is sought for which passes the post-layout validation test. Circuit sizing primarily comprises of two components: a search engine and a performance estimator. Stochastic combinatorial optimization techniques are used for exploring the design space. For each candidate design explored by the search engine, the circuit performance is estimated. Typically, the performance estimation time dominates the overall synthesis time. Most commercial approaches deploy a simulator-in-loop approach to the sizing problem due to the high accuracy desired from the estimation process. We propose two techniques for replacing the simulator with accurate and efficient performance models. Since the performance models allow a very quick evaluation of the circuit performance, their use helps in drastically reducing the time complexity of sizing. Unlike the existing macro-model driven sizing techniques, the proposed approaches guarantee to obtain accurate simulator validated design solutions. We propose a unified system which aims to resolve both the problems of computational complexity of performance estimation and performance closure at the layout stage in the same flow. The proposed system combines the ideas of parasitic modeling, design optimization in presence of worst case parasitics corners and performance macromodeling put forth in this dissertation to create high quality designs efficiently.
Advisors/Committee Members: Vemuri, Dr. Ranga.
Keywords: Analog, Radio-frequency, Circuit Synthesis, Layout Parasitics, Performance Modeling, Parasitic Estimation and Modeling, Layout-Aware Synthesis, Circuit sizing, Parasitic Corners, Yield Optimization, Parasitic Capacitances, Dynamic Performance Macromodel
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2.
Alqadah, Faris.
Clustering of Multi-Domain Information Networks.
Degree: PhD, Engineering : Computer Science and Engineering, 2010, University of Cincinnati
► Clustering is one of the most basic mental activities used by humans…
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▼ Clustering is one of the most basic mental activities used by humans to handle the huge amount of information they receive every day. As such, clustering has been extensively studied in different disciplines including: statistics, pattern recognition, machine learning and data mining. Nevertheless, the body of knowledge concerning clustering has focused on objects represented as feature vectors stored in a single dataset. Clustering in this setting aims at grouping objects of a single type in a single table into clusters using the feature vectors. On the other hand, modern real-world applications are composed of multiple, large interrelated datasets comprising distinct attribute sets and containing objects from many domains; typically such data is stored in an information network. The types of patterns and knowledge desired in these applications goes far beyond grouping similar homogeneous objects, but rather involves unveiling dependency structures in the data in addition to pinpointing hidden associations across objects in multiple datasets and domains. For example consider an information network that contains the domains of authors, papers and conferences. Two authors a1 and a2 may work in the same research field but never publish in the same conference. Hence clustering only the domains of authors and conference would fail to place a1 and a2 in the same cluster; however considering the entire information network would reveal a hidden link via the papers domain, placing a1 and a2 in the same cluster. This form of relational clustering is essential for knowledge discovery in several applications such as: bioinformatics, social networking, and recommender systems. Information-network clustering advances knowledge discovery in two manners. First, hidden associations amongst objects from differing domains are unveiled, leading to a better understanding of the hidden structure of the entire network. Second, local clusters of the objects within a domain are sharpened and put into greater context, leading to more accurate local clustering. In order to extract knowledge of this form, information network clustering algorithms must consider 1) overlapping clusters and 2) a clustering structure that relates the clusters. In this dissertation we develop a framework and several algorithms for information network clustering by leveraging the above two fundamental aspects that facilitate knowledge discovery. Current state-of-the-art information network clustering algorithms have had relative success in addressing the computational challenge of high dimensional data; however, the majority of these approaches have not addressed the fundamental aspects of overlapping clusters and clustering structure. In this dissertation, we address the information-network clustering problem from a fresh perspective and introduce a novel framework based on Formal Concept Analysis (FCA). Based on mathematical order theory, in particular, the theory of complete lattices, FCA provides a rich theoretical basis for investigating and structuring overlapping relational clustering in a single dataset. Shortcomings of previous methods were overcome by extending FCA to information networks, yielding effective and efficient information network clustering algorithms. Several empirical evaluations performed on a large variety of real-world information networks reveal that the FCA-based algorithms work more effectively and efficiently than the current state of the art.
Advisors/Committee Members: Bhatnagar, Raj.
Subjects: Computer science
Keywords: Data Mining; Clustering; Information Networks; Subspace Clusters; Bi-Clustering; Formal Concept Analysis
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3.
BADAOUI, RAOUL.
APPROACHES FOR PARASITIC-INCLUSIVE SYMBOLIC CIRCUIT REPRESENTATION AND EXTRACTION FOR SYNTHESIS.
Degree: PhD, Engineering : Computer Science and Engineering, 2005, University of Cincinnati
► Layout-induced parasitics have significant effects on the behavior of circuits in general…
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▼ Layout-induced parasitics have significant effects on the behavior of circuits in general and the performance of high-frequency analog ones in particular. To achieve parasite-inclusive performance-closure, layout-aware circuit synthesis methodologies are beginning to emerge. In layout-in-the-loop synthesis methodologies, performance analysis is based on the generation of a concrete layout for the explored circuit sizes. A parasite-inclusive circuit is extracted from the layout using a standard extractor and is analyzed using a simulator to determine whether the required constraints are met. The purpose of layout generation during the synthesis process is solely to determine the layout-induced effects in terms of device and interconnect parasites in the extracted circuit in order to perform accurate, layout-aware performance analysis. If the parasites could be estimated or determined otherwise, there would be no need for layout generation. Various approaches of estimating parasitics lack the correctness that would only come from examining the layout itself. The proposed approach tries to include the exactness of the layout to be generated without actually generating it. It relies on using pre-generated structures for the specified un-sized circuit; these structures are generated before synthesis, they contain the information that a layout would have provided to a synthesis process if it was to be generated. This information contains extraction specifics for modules, location of modules and routing characteristics. Pre-Layout Extraction: The concept of Pre-Layout Extraction shall be used to cover the extraction specific information of modules present in the circuit. It is achieved using a high-level language MSL (Module Specification Language) for the specification of parameterized, topology-specific circuit extractors. Upon compilation, the MSL program yields an executable module which generates the extracted circuit containing parasitics, passive and active devices when given specific sizes. This is done without ever generating a layout. Multi-Placement Structures: For the placement specification of the layout, Multi-Placement Structures shall be used. The proposed approach aims at retaining the benefits of both optimization-based techniques and layout templates techniques: a fast instantiation time of layout for layout-inclusive synthesis and various placement possibilities for various input sizes. ( No restriction to a single, pre-defined template ). It consists of a one-time generation of a multi-placement structure for a specific unsized circuit. The obtained structure would be used in a layout-inclusive synthesis process in the following manner: It is provided with numerical sizes from a sizing algorithm tool and returns a specific floor-plan for the circuit. For different sizes given, the aim is to have the best floor-plan returned depending on the specified sizes. Multi-Variant Routing: The remaining part of a layout description known as routing shall be handled using the proposed idea of Multi-Variant Routing. This method follows the same line of thought as its corresponding one in the placement field. It consists of a one-time generation of a Multi-Variant Routing Structure that would instantiate distinct routing schemes for distinct specified sizes and modules positions. Depending on the size of the modules in the circuit, and on their locations instantiated using the Multi-Placement Structure, the Multi-Variant Routing Structure shall be able to produce the most efficient routing scheme for the proposed circuit. Its power relies on a one-time intelligent search accomplished before synthesis, while building the structure. Depending on the locations and the sizes of the modules in the circuit, the nets in the circuit are attached to a multiple-possibility path that is controlled by the dynamic feature of changin channels and blocks’ sizes. The combination of these three described novel methods of layout approaches can be very beneficial to the synthesis of circuits and specially analog ones. It is expected to introduce a speedup factor varying from 4 to 5 with comparison to layout-inclusive synthesis approaches while having the quality of layout exploration not found in template-based approaches.
Advisors/Committee Members: Vemuri, Dr. Ranga.
Keywords: vlsi; analog vlsi; routing; placement; extraction; pre-layout extraction
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4.
BANERJEE, SANDIPTO.
DATA WAREHOUSE SCHEMA EVOLUTION WITH EXTENDED HIERARCHY SEMANTICS.
Degree: PhD, Engineering : Computer Science and Engineering, 2007, University of Cincinnati
► A data warehouse technology provides a way to visualize data in a…
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▼ A data warehouse technology provides a way to visualize data in a form that helps in the decision making process. This visualization is provided by a multi-dimensional schema that captures the user needs in terms of data content, constraints on data, and views of data. User requirements can change over a period of time and this causes the schema to be redesigned from scratch. Redesigning a schema is an expensive process in terms of resources and time. A solution to this problem is designing a schema evolution process that helps a schema to evolve. Models for conceptual design of data warehouse schemas have been proposed by researchers, but none have provided a formal definition of semantics to support schema evolution. As a first step to the schema evolution process, we introduce a formal model that captures the conceptual modeling features of a data warehouse. The conceptual modeling features are categorized as core and advanced features. Previously authors have defined the core features to capture simple semantic information of a multi-dimensional schema. In our work we extend the semantics of our model to represent complex information by defining advanced features such as non-strict, non-onto, non-covering and multiple hierarchies. Model constraints are defined to maintain integrity when a schema evolves over a period of time. In the second step we design schema evolution operators that help to make changes to a multi-dimensional schema. To visualize these two steps we implement a software tool that helps to create semantically correct schemas and understand the impact of evolution over a schema with extended semantics via stored procedures and triggers for integrity enforcement. We further extend the formal model to support instance data and map the relationship between these instances in a lattice framework. When a schema evolves, the aggregations of the new instance data can be derived from the aggregation of instances of the original schema thus saving resources and improving the decision making capability of a data warehouse.
Advisors/Committee Members: Davis, Dr. Karen.
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5.
BEOHAR, SHRUTI.
DESIGN AND IMPLEMENTATION OF SESSION-BASED DIFFUSION FOR SENSOR NETWORKS.
Degree: MS, Engineering : Computer Science and Engineering, 2006, University of Cincinnati
► Study of the query workload in some sensor network applications shows that…
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▼ Study of the query workload in some sensor network applications shows that querying in a sensor network environment can be relative, relative to what was sensed earlier in the network. As an experiment progresses, experimenters focus on regions of the network in which interesting information is sensed. Queries need to be targeted to these specific regions, instead of being flooded into the network. We note that there is a need to be able to steer queries to such interesting regions. We find that this can be achieved by caching the results gathered from the network within the network itself. The network sustains results for a certain period of time, which we call the session. The cached results serve as decision points and provide hints on whether forwarding a query further into the network will be beneficial. The queries that are addressed to a region are termed relative queries. Relative queries, unlike geographic queries, are not targeted to a geographic location but depend on the data sensed by queries sent earlier into the session. We describe a heterogeneous network structure consisting of certain high capacity gateway nodes that take up the responsibility for caching the data sensed by the nodes in their cluster. The gateway nodes exercise control over which relative query is forwarded to what extent in their clusters. The scheme is implemented as a diffusion filter, so it inherits the benefits built into the diffusion infrastructure. We envision the possibility of reconfiguring only specific areas of the network. This reconfiguration is localized to the area that sensed the data that triggered the change. We claim that our scheme can be used to reconfigure selected areas of the network. We present the results from experiments done with different numbers of relative queries, different values for the session period and different topologies. We conclude by describing how this work can be extended to build intelligence into the network.
Advisors/Committee Members: Purdy, Dr. Carla.
Subjects: Computer Science
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6.
BHADURI, AMITAVA.
INDUCTIVE AND CAPACITIVE AWARE METHODOLOGIES FOR PHYSICAL AND CIRCUIT SYNTHESIS OF HIGH-SPEED DIGITAL AND RF CIRCUITS.
Degree: PhD, Engineering : Computer Science and Engineering, 2005, University of Cincinnati
► Computer-aided design in VLSI is a continuously evolving subject, with new algorithms…
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▼ Computer-aided design in VLSI is a continuously evolving subject, with new algorithms and solutions constantly modifying the established norms in order to accommodate efficient strategies to make CAD principles strong at an early phase of design abstraction. The same principle also applies to the routing phase in the physical design of VLSI circuits. There have been several attempts to innovate novel routing methodologies and make it parasitic aware. This awareness in the routing paradigm is important in high-frequency designs, since inductive and capacitive crosstalk that often proved to be crucial in the performance of digital and analog circuits were ignored in previous design attempts. We added an important flavor to make the interconnect-centric routing more meaningful. Realizing the importance of self and mutual inductance and coupling capacitance between neighboring wires, we introduced a routing approach based on higher order moment metrics, which captures the inductive and capacitive parasitics to form a cost function comprising of a mathematical expression. Minimizing the cost allowed us not only to obtain routes that are inductive and capacitive aware but also that produced the least ringing and delay during signal propagation. To make the route cost function even more robust and efficient, we introduced a concept of parasitic transformation on the universal RLC template required by the moment-driven cost function. Besides making the routing technique parasitic-aware, we also made the routing methodology suited towards faster convergence, in line with the requirement of an efficient CAD tool. A constraint-driven non-linear algorithm that satisfies the design rule requirements in addition to minimizing the moment-driven cost function using non-linear algorithm, has been developed to serve this purpose. Layout inclusive synthesis strategies have been present in the domain of Analog and RF synthesis for quite some time. Introducing capacitive and on-chip inductor parasitics helped to bring the parasitic awareness during synthesis and prevented the expensive re-design loop between fabrication and design specification from happening. In order to give the synthesis technique a new dimension and a more refined approach, we implemented a quasi-static extraction strategy in order to extract the resistive, self and mutual inductive parasitics of on-chip inductors and interconnects, within the synthesis flow. Previous attempts, which were ignorant of complete self and mutual inductive and capacitive parasitics of on-chip inductors and interconnects, benefited from this full parasitic extraction technique, thereby giving a fruitful closure to RF circuit synthesis by making the design layout-aware. We also extended the moment-driven routing methodology to the RF circuit synthesis domain, in order to make the routing process at the layout inclusion stage intelligent in terms of parasitic awareness, and efficient, by not transferring the burden of bad routing decisions to the synthesis engine. Coupled with this idea integration, we also included a proven fast and accurate parasitic device modeling strategy to obviate complicated layout generation and extraction steps required in the layout-inclusive RF circuit synthesis. The device parasitic extraction using this technique is based on multivariate interpolation strategy and led to faster convergence time for RF LNA synthesis.
Advisors/Committee Members: VEMURI, Dr. RANGA.
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7.
BISWAS, RATNABALI.
Query Processing and Link Layer QoS Provisioning Mechanisms for Wireless Sensor Networks.
Degree: PhD, Engineering : Computer Science and Engineering, 2006, University of Cincinnati
► Recent advances in MEMS (micro-electro-mechanical systems) and radio technology has enabled development…
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▼ Recent advances in MEMS (micro-electro-mechanical systems) and radio technology has enabled development of low-cost wireless sensor networks (WSNs). Due to their ease of deployment and ad hoc connectivity, WSNs are emerging as a promising tool for a wide range of applications. Each sensor node is equipped with programmable computing, multiple-parameter sensing and wireless communication capability. Sensor nodes are however, constrained in terms of available resources such as energy, storage and computation. Such limitations make it really challenging to realize a reliable WSN infrastructure that can efficiently process different types of user queries. The objective of this dissertation is to develop energy-efficient mechanisms for enabling query processing in WSNs, despite unreliable nature of the wireless medium. The first part of this dissertation focuses on designing energy-efficient architectures for processing different kinds of user queries. Queries in WSNs can be broadly classified as location-based queries and attribute-based queries. To enable processing of long-running location-based queries, the recent trend is to evaluate queries within the WSN, so as to reduce the overall communication and energy consumption of the WSN. The in-network query processing architecture proposed in this dissertation determines optimal placement of query operators within a WSN in a decentralized manner and also adapts to continual changes in network and data properties. On the other hand, the recent trend in processing attribute-based queries is employing data-centric storage schemes that eliminate the need for flooding the WSN. In this dissertation, a novel data-centric storage scheme has been developed to determine rendezvous points for storing individual attributes depending on their correlation with other attributes. Both analytical and simulation studies have been performed to identify the conditions under which the proposed architecture is useful. The second part of this dissertation focuses on designing mechanisms for ensuring reliable and timely delivery of the sensed data. WSNs are generally deployed in inhospitable terrains and consist of a dense deployment of sensor nodes. Furthermore, wireless communication is inherently unpredictable and error-prone. Hence, it is imperative to design an efficient medium access control (MAC) protocol that facilitates guaranteed delivery of data over unreliable wireless links. In this dissertation, such an on-demand reliable MAC protocol has been proposed and its superior performance in terms of reliability, latency and scalability has been demonstrated. Furthermore, we have also proposed another MAC protocol that is both energy-efficient and reliable. The energy-efficiency of the proposed MAC protocol has been achieved by switching the sensor nodes to sleep mode when they are not involved in data communication. However in doing so, measures have been taken to avoid problems like overemitting, excessive latency and frequent changes of the radio state. Thus, our proposed MAC protocol reliably delivers sensed data with minimum power consumption, thereby attempting to reach the desirable objectives of WSNs.
Advisors/Committee Members: Agrawal, Dharma P.
Keywords: Data Centric Storage, Medium Access Protocol, Query Processing, Wireless Sensor Networks
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8.
CAVALCANTI, DAVE ALBERTO TAVARES.
INTEGRATED ARCHITECTURE AND ROUTING PROTOCOLS FOR HETEROGENEOUS WIRELESS NETWORKS.
Degree: PhD, Engineering : Computer Science and Engineering, 2006, University of Cincinnati
► One of the main challenges in next generation wireless networks is to…
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▼ One of the main challenges in next generation wireless networks is to integrate heterogeneous wireless technologies to provide seamless connectivity, with guaranteed Quality of Service (QoS), to mobile users “anytime, anywhere and with any device”. In this dissertation, we investigate the problem of integrating cellular networks and Wireless Local Area Networks (WLANs) with the multi-hop communication paradigm used in Mobile Ad hoc Networks (MANETs) to exploit all the connectivity alternatives available to different types of Mobile Stations (MSs). We propose an integrated architecture based on three basic functionalities, namely, topology discovery, gateway discovery, and link quality estimation. We combine these three functionalities into an integrated routing mechanism that exploits all connectivity alternatives available in a generic heterogeneous scenario. Then, we provide a simulation-based analysis of our architecture and integrated routing mechanism in different heterogeneous networking scenarios. Our results show improvements in network’s capacity and coverage achieved by our architecture as compared to isolated networks. The results also highlight the importance of the link quality estimation in providing QoS to users, as well as indicate that multi-hop links can be exploited in a controlled network configuration, but the QoS in multi-hop routes cannot be always guaranteed. Furthermore, we address the problem of selecting the best connectivity opportunity for a given service type based on the applications’ QoS requirements, as well as on the network condition and user mobility profile. We propose the Connectivity opportunity Selection Algorithm (CSA) that allows MSs to select the connectivity opportunity most appropriate for a given type of service and mobility profile. Furthermore, we describe how our proposed selection algorithm can be introduced into the IEEE 802.21 standard for Media Independent Handover services.
Advisors/Committee Members: Agrawal, Dr. Dharma P.
Subjects: Computer Science
Keywords: Heterogeneous Wireless Networks.; Routing Protocols for Heterogeneous Wireless Networks; Multi-hop communications in integrated wireless networks; network selection; always best connectivity
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9.
CHATHA, KARAMVIR SINGH.
SYSTEM-LEVEL COSYNTHESIS OF TRANSFORMATIVE APPLICATIONS FOR HETEROGENEOUS HARDWARE-SOFTWARE ARCHITECTURES.
Degree: PhD, Engineering : Computer Science and Engineering, 2001, University of Cincinnati
► Transformative applications are computationally intensive applications like image compression and decompression algorithms.…
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▼ Transformative applications are computationally intensive applications like image compression and decompression algorithms. Embedded system implementations of transformative applications typically consist of multiple hardware and software processing elements. The objective of the research presented in this dissertation is to develop and implement innovative computer-aided design techniques for system-level cosynthesis of transformative applications for heterogeneous hardware-software architectures. As part of the research 1) a specification library, 2) an internal graph based format, and design tools for 3) latency minimization and 4) throughput maximization are developed. The specification library, graph format and optimization tools are encased in a system-level design environment called STELLAR. This dissertation presents the STELLAR environment for system-level hardware-software cosynthesis of transformative applications.The specification library called NOVA is based on an object-oriented approach and contains a collection of C++ classes.NOVA provides classes for specification of functionality, architecture and performance constraints. NOVA models the application functionality as a hierarchical, control and dataflow based task graph. It is an executable specification that can be functionally verified after compilation with the standard gcc compiler. NOVA provides constructs for specifying latency and throughput constraints on the application. It also provides constructs for specifying the system architecture that can include general purpose software processors, field programmable gate arrays, application specific integrated circuits and memory elements. The library supports specification of area constraints, reconfiguration times, memory sizes and memory widths of the various architecture elements. The internal graph format called NEBULA is derived from the NOVA specification. NEBULA captures the essential behavioral, structural and performance information of the application that is relevant for system-level optimization. The latency minimization tool called MAGELLAN and throughput maximization tool called ULYSSES are heuristic approaches for mapping the hierarchical control and dataflow based task graphs on heterogeneous architecture templates. MAGELLAN uses an iterative technique of closely linked hardware-software partitioning and scheduling. ULYSSES includes retiming transformation along with partitioning and scheduling. Both of them apply the partitioner and scheduler in a hierarchical top down manner. They optimize deterministic loop constructs by applying clustering, unrolling and pipelining. The number of actual hardware/software implementations of a function call in the task graph are optimized by resource sharing. MAGELLAN also considers speculative execution for conditional constructs. The techniques are validated by extensive experimentation with a realistic application. Additionally the quality of the results is evaluated by comparing with optimal approaches. Experiments are also conducted with synthetic task graphs to evaluate the run times of the techniques.
Advisors/Committee Members: Vemuri, Dr. Ranga.
Keywords: system-level design; hardware-software cosynthesis; hardware-software partitioning; pipelined scheduling; retiming transformation
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10.
CHENG, YI.
Security Mechanisms for Mobile Ad Hoc and Wireless Sensor Networks.
Degree: PhD, Engineering : Computer Science and Engineering, 2008, University of Cincinnati
► Wireless Ad Hoc Networks have emerged as an advanced networking paradigm based…
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▼ Wireless Ad Hoc Networks have emerged as an advanced networking paradigm based on collaborative efforts among multiple self-organized wireless communication devices. Without the requirement of a fixed infrastructure support, wireless ad hoc networks can be quickly deployed anywhere at any time when needed. The decentralized nature, minimal configuration and quick deployment of wireless ad hoc networks make them suitable for various applications, from disaster rescue, target tracking to military conflicts. Wireless ad hoc networks can be further categorized into mobile ad hoc networks (MANETs), wireless sensor networks (WSNs), and wireless mesh networks (WMNs) depending on their applications.Security is a big challenge in wireless ad hoc networks due to the lack of any infrastructure support, dynamic network topology, shared radio medium, and resource-constrained wireless users. Most existing security mechanisms applied for the Internet or traditional wireless networks are neither applicable nor suitable for wireless ad hoc network environments. In MANETs, routing security is an extremely important issue, as the majority of the standard routing protocols assume non-hostile environments. Once deployed in a hostile environment and working in an unattended mode, existing routing protocols are vulnerable to various attacks. To address these concerns, we propose an anonymous secure routing protocol for MANETs in this dissertation, which can be incorporated with existing routing protocols and achieve enhanced routing security with minimum additional overheads. In WSNs, key distribution and management is the core issue of any security approaches. Due to extremely resource-constrained sensor nodes and lack of any infrastructure support, traditional public-key based key distribution and management mechanisms are commonly considered as too expensive to be employed in WSNs. In this dissertation, we propose two efficient pairwise key pre-distribution and management mechanisms for both distributed and hierarchical large-scale WSNs, which enable establishing secure links between any two sensor nodes located within their communication range. As we know, sensing and communication are two fundamental characteristics of WSNs, and they cannot be addressed separately. Existing work on sensing coverage mainly focus on how to use the minimum number of sensors to achieve a required coverage, while security constraints are not sufficiently addressed. We propose an effective key distribution approach for randomly deployed WSNs, based on random graph theory and a realistic random key pre-distribution mechanism, in order to achieve both robust sensing coverage and secure connectivity simultaneously in a hostile deployment environment.
Advisors/Committee Members: Agrawal, Dharma.
Subjects: Communication; Computer science
Keywords: Wireless Ad Hoc Network, Mobile Ad Hoc Network (MANET), Wireless Sensor Network (WSN), Routing, Security, Cryptography, Key Management, Distributed Wireless Network, Hierarchical Wireless Network, Sensing Coverage, Secured Connectivity
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11.
CHEN, HANG.
RESOURCE MANAGEMENT SCHEMES IN WIRELESS AND MOBILE NETWORKS.
Degree: PhD, Engineering : Computer Science and Engineering, 2004, University of Cincinnati
► A rapid increase in the size of the wireless mobile community and…
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▼ A rapid increase in the size of the wireless mobile community and its demands for high-speed multimedia communications have been subjected to rather limited spectrum resource that have been allocated as per international agreements. Efficient radio resource management is of paramount importance due to these increasing demands. Good resource management schemes should support as many as possible mobile users while maintaining the necessary QoS. First, the notions of QoS for wireless and mobile networks are very different from fixed networks due to the restrictions and limitations of the air interface. Moreover, the next generation wireless and mobile networks have been designed to support true convergence of multi-class services that have distinct characteristics and performance requirements. In this dissertation, several efficient resource allocation schemes have been developed to improve the system performance, including the near optimal channel partitioning scheme, priority cutoff scheme, adaptive channel allocation scheme and power-based call admission scheme for CDMA system. A comprehensive set of QoS metrics is also defined and analytical models are carried out to derive the closed form expressions of these QoS parameters and to investigate the impact of resource management schemes on the system performance. Extensive simulation results show that the proposed schemes outperform existing resource allocation schemes under various scenarios. Furthermore, not only schemes for resource management in integrated wireless and mobile networks are provided in this dissertation, but also solutions for future generation wireless and mobile networks. Finally, we conclude this dissertation with some promising future work in the area of future generation wireless and mobile networks.
Advisors/Committee Members: Agrawal, Dr. Dharma.
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12.
Chetlur, Malolan.
Causality Representation and Time Warp Optimizations.
Degree: PhD, Engineering : Computer Science and Engineering, 2007, University of Cincinnati
► Time Warp optimistic protocols are exposed to performance degrading cascading rollbacks. In…
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▼ Time Warp optimistic protocols are exposed to performance degrading cascading rollbacks. In addition, optimistic simulation has the potential to reach an inconsistent state due to lagging rollbacks, thereby resulting in system failures. These issues are due to short-sighted reactive measures employed during the rollback process. The above mentioned risks can be avoided with the knowledge of causality. This study presents new optimizations that exploit additional knowledge gleaned from causality information in Time Warp simulations. The causality relation among events is captured and disseminated by a logical clock framework and this information is exploited in optimizations. This thesis explores causal dissemination frameworks and optimizations using these frameworks. First, a theoretical logical clock framework named Total Clocks (TC) is presented. This framework captures and disseminates strong causality relation among events in virtual time paradigm. The detailed clock update rules and the properties of TC are established. The utility of this framework is demonstrated with the design of a distributed cancellation technique to avoid cascading and inter-related rollbacks. In addition, a proof of correctness of this cancellation technique is presented. The TC framework is not scalable and therefore, this study address its scalability issues with the design of Plausible Total Clocks (PTC). The PTC is a constant size clock capturing weak causality relation among events and its size is independent of the number of simulation objects. A proactive cancellation mechanism using the PTC framework to detect and avoid cascading rollbacks and a proof of correctness of this technique are presented. In addition, this proactive cancellation mechanism is implemented in the WARPED simulation kernel. Empirical results of this implementation running on 32 processors show a performance improvement between 10% - 15% for simulations exhibiting cascading rollbacks. To further demonstrate the utility of causal dissemination framework, two new Time Warp optimizations exploiting causality are presented. The first optimization is a fossil identification technique that is independent of GVT. A proof of correctness of this new fossil collection technique is presented. The second optimization is a causality based scheduling mechanism and this scheduling mechanism running on 32 processors show a performance improvement between 10% - 15%.
Advisors/Committee Members: Wilsey, Dr. Philip A.
Subjects: Computer Science
Keywords: Time Warp; Logical Time; Plausible Clocks
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13.
CORDEIRO, CARLOS DE MORAIS.
MEDIUM ACCESS CONTROL PROTOCOLS AND ROUTING STRATEGIES FOR WIRELESS LOCAL AND PERSONAL AREA NETWORKS.
Degree: PhD, Engineering : Computer Science and Engineering, 2003, University of Cincinnati
► Recent advances in portable computing and wireless technologies are opening up exciting…
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▼ Recent advances in portable computing and wireless technologies are opening up exciting possibilities for the future of wireless mobile networking. More notably, Wireless Local and Personal Area Networks (WLANs and WPANs) technologies are expected to revolutionize the way we live. Given their unprecedented importance, in this dissertation we investigate and suggest new solutions in the context of WLANs and WPANs systems. In the world of WLANs, we study its major representative, namely, the IEEE standard 802.11, while we explore the Bluetooth technology as it is the most prominent solution in the world of WPANs. In the field of Bluetooth, we have identified key issues and made considerable contributions. We have carried out a detailed analytical and simulation analysis of radio interference impact on Bluetooth and proposed ways of mitigating it, such as a novel interference-aware packet segmentation protocol (IBLUES). Moreover, we also introduce an integrated IEEE 802.11 and Bluetooth architecture (BlueStar), which enables efficient information interchange between these two widely used technologies. BlueStar is analyzed in great detail and, among other things, it features a new coexistence method between IEEE 802.11 and Bluetooth which employs a novel combination of carrier sense and adaptive frequency hopping. Next, to handle the inefficiency of the current Bluetooth master/slave communication paradigm, we propose a novel QoS-driven dynamic slot assignment and piconet partitioning algorithms. In the context of IEEE 802.11, we initially investigate advanced MAC-based routing strategies. These strategies, referred to as COPAS (contention-based path selection), are intentionally devised and observed to boost TCP performance over the multi-hop type of IEEE 802.11 ad hoc networks, giventhat TCP is by far the most important and widely used transport protocol in today’s networks. Finally, we design and evaluate a new power control MAC protocol for spatial reusability over ad hoc networks, which is observed to considerably outperform existing MAC protocols. We conclude with some promising future work in the areas of both Bluetooth and IEEE 802.11.
Advisors/Committee Members: Agrawal, Dr. Dharma.
Subjects: Computer Science
Keywords: wireless; Bluetooth; IEEE802.11; network; performance evaluation
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14.
DHARMATILLEKE, SAMAN MANGALA.
MEMS PROTOTYPICAL SYSTEM INTEGRATION AND PACKAGING FOR A GENERIC MICROFLUIDIC SYSTEM.
Degree: PhD, Engineering : Computer Science and Engineering, 2001, University of Cincinnati
► This work describes the development of a new portable fully automated microfluidic…
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▼ This work describes the development of a new portable fully automated microfluidic system that fits into the palm of a hand, to perform a magnetic bead-based sandwich immunoassay in order to detect airborne bio-organisms (such as biological warfare agents). The magnetic beads were coated with a polymer to which a dendrimer-antibody conjugate had been attached to form the basis of a "sandwich" immunoassay for sensing bio molecules. Three systems were designed and fabricated using different materials as the substrate: (1) A system was fabricated on a glass-on-silicon motherboard realized by etching the micro channels directly into a silicon wafer and capping the channels with a glass wafer by anodically bonding glass-to-silicon; (2) a system was assembled by using biocompatible silicone tubing for interconnections between the devices; and (3) a silicone polymer system was formed which has embedded micro channels in polymer. The glass-on-silicon system consists of four collapsible reservoirs for reagent storage, made of very thin Teflon(tm); an array of zero dead volume "collapsible" membrane type valves; two unique magnetic curtain magnetic particle separators; a micro wire electrode or IDA (inter digitated array) for detection; a flow sensor; and a peristaltic pump consisting of three membrane type valves placed in series. The system using the biocompatible silicone tubing consists of four polyethylene reservoirs, an array of zero dead volume pinch valves, two magnetic curtain magnetic particle separators, a micro wire electrode or IDA for detection, a flow sensor and a valveless mini rotary pump to pull the reagents through the microfluidic system. The silicone polymer system consists of four polyethylene reservoirs, an array of zero dead volume pinch valves, two magnetic curtain magnetic particle separators, an IDA for detection and a valveless mini rotary pump to pull the reagents through the microfluidic system. All these systems have their associated electronics. This work precedes the next step, which is an all MEMS monolithic system "on-a-chip", although it already has the smallest working components achieved in this multi-team project. This work was funded by the Microsystems Technology Office of the Defense Advanced Research Project Agency (DARPA-MicroFlumes Program) under contract AF F30602-97-2-0102.
Advisors/Committee Members: Henderson, Dr. H. Thurman.
Keywords: microfluidic; lab on a chip; magnetic bead separator; anodic bonding
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15.
DING, MENGMENG.
REGRESSION BASED ANALOG PERFORMANCE MACROMODELING: TECHNIQUES AND APPLICATIONS.
Degree: PhD, Engineering : Computer Science and Engineering, 2006, University of Cincinnati
► Optimization based analog circuit sizing opens a new page for computer aided…
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▼ Optimization based analog circuit sizing opens a new page for computer aided design of analog integrated circuits. While differing in implementation details, the sizing tools usually include two main modules: an optimization engine and a module for performance parameter evaluation. The latter often contributes to the bulk of total computational time when a transistor level circuit simulator is used to obtain performance parameters. This motivates us to develop fast performance macromodels.Regression based techniques, when applied to performance macromodeling, have obvious advantages over other approaches: higher degree of automation, no need for simulator whatsoever, applicable to any performance parameter and topology. On the other hand, regression techniques usually suffer from “the curse of dimensionality”, which refers to the phenomenon that the sample size needed to cover a high dimensional space grows exponentially with the dimension. This thesis provides a few novel techniques to cope with this problem based on the specific needs by analog performance macromodeling, falling into two categories: adaptive sampling and design space reduction. Initial effort has been dedicated to developing an adaptive sampling algorithm to reduce training set size while maintaining high model accuracy. The proposed adaptive sampling algorithm is called adaptive grid refinement algorithm. The algorithm first constructs a regression model in the entire design space, a hypercube, using training data set generated from a two level full factorial design. The hypercube is then split into equal-sized smaller hypercubes if the model has error exceeding user defined bound. Within each smaller hypercube a local regression model is constructed and validated. Splitting stops only if all the local models have validation errors within the error bound. The final model is a set of local regression models. Although it is desirable to model the entire design space accurately, only part of the design space called the feasible design space is worth exploring by an analog sizing tool. A feasibility model is needed to identify the feasible design space. Feasibility modeling is treated as a two-class classification problem in our case. The small size of the feasible design space, however, challenges the state-of-the-art classification techniques such as Support Vector Machines when uniform randomly distributed instances are used for model training. We thus propose an active learning scheme to improve the feasibility classifier’s accuracy more efficiently. The performance regression macromodels are built and validated within the feasible design space. Experiments show that they are more accurate compared to those valid within the entire design space when equal sized training sets are used. The resulting performance macromodel is essentially a combined model: a feasibility classifier and a set of performance regression models. The third technique is designed to further reduce modeling cost of the combined model. More efficient feasibility model generation is achieved by introducing a sequential design space decomposition algorithm. Performance regression models are developed similarly. The sequential design space decomposition algorithm decomposes the initial design space into smaller partitions and constructs one feasibility classifier for one subsequent significant partition that includes most of the feasible designs. The final feasibility model is composed of a set of classifiers, each of which has its own applicable region. By sequentially decomposing the design space and exploring the significant partitions, we are able to build feasibility model of high precision with much lower modeling cost. The above three techniques make the core of a semi-automated tool for analog performance macromodel generation. We demonstrate two applications of analog performance macromodels: analog circuit sizing and performance tradeoff analysis. Several opamp topologies have been sized to meet various design goals. The sized circuits are verified against the transistor level circuit simulator Hspice. The experimental results show that by using analog performance Macromodels even a simple simulated annealing algorithm can find designs that meet or approximately meet the design goals within minutes. We also show that performance tradeoff analysis of a given circuit topology can be done efficiently with the aid of analog performance macromodels.
Advisors/Committee Members: Vemuri, Dr. Ranga.
Keywords: analog performance macromodeling; analog circuit sizing; adaptive sampling; active learning; regression; classification
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16.
FISTER, JUSTIN M.
CORRELATION ANALYSIS OF ON-PAGE ATTRIBUTES AND SEARCH ENGINE RANKINGS.
Degree: MS, Engineering : Computer Science and Engineering, 2007, University of Cincinnati
► Despite sophisticated search engine algorithms designed to eliminate irrelevant content, many Internet…
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▼ Despite sophisticated search engine algorithms designed to eliminate irrelevant content, many Internet content providers with valuable information are unable to achieve visibility in the search engine results due to many factors including lack of information, misinformation, and search engine trade secrets. Furthermore, a survey of information on the topic yields questionable advice unsubstantiated by research and statistical analysis. Consequently, this thesis addresses some of the problems facing content providers by providing relevant statistics, as well as a simple research framework allowing content providers to easily extend this research and more fully understand the search engine ranking algorithms. Due to the large scope of the search engine ranking topic, this thesis focuses solely on examining the relationship between on-page attributes and search result ranking. Nevertheless, the research framework presented in this thesis can be altered to extend this research beyond the analysis of on-page attributes.
Advisors/Committee Members: Cheng, Dr. Yizong.
Keywords: search engine rankings, search engine optimization
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17.
Ghosh, Chittabrata.
Innovative Approaches to Spectrum Selection, Sensing, and Sharing in Cognitive Radio Networks.
Degree: PhD, Engineering : Computer Science and Engineering, 2009, University of Cincinnati
► In a cognitive radio network (CRN), bands of a spectrum are shared…
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▼ In a cognitive radio network (CRN), bands of a spectrum are shared by licensed (primary) and unlicensed (secondary) users in that preferential order. It is generally recognized that the spectral occupancy by primary users exhibit dynamical spatial and temporal properties. In the open literature, there exist no accurate time-varying model representing the spectrum occupancy that the wireless researchers could employ for evaluating new algorithms and techniques designed for dynamic spectrum access (DSA). We use statistical characteristics from actual radio frequency measurements, obtain first- and second-order parameters, and define a statistical spectrum occupancy model based on a combination of several different probability density functions (PDFs). One of the fundamental issues in analyzing spectrum occupancy is to characterize it in terms of probabilities and study probabilistic distributions over the spectrum. To reduce computational complexity of the exact distribution of total number of free bands, we resort to efficient approximation techniques. Furthermore, we characterize free bands into five different types based on the occupancy of its adjacent bands. The probability distribution of total number of each type of bands is therefore determined. Two corresponding algorithms are effectively developed to compute the distributions, and our extensive simulation results show the effectiveness of the proposed analytical model. Design of an efficient spectrum sensing scheme is a challenging task, especially when false alarms and misdetections are present. The status of the band is to be monitored over a number of consecutive time periods, with each time period being of a specific time interval. The status of the sub-band at any time point is either free or busy. We proved that the status of the band over time evolves randomly, following a Markov chain. The cognitive radio assesses the band, whether or not it is free, and the assessment is prone to errors. The errors are modeled probabilistically and the entire edifice is brought under a hidden Markov chain model in predicting the true status of the band. After spectrum sensing, our research direction is on spectrum sharing using cooperative communication. We discuss allocation strategies of unused bands among the cognitive users. We introduce a cooperative N-person Game among the N cognitive users in a CRN and then identify strategies that help achieve Nash equilibrium. When licensed users arrive in any of those sub-bands involved in unlicensed user communication, the affected cognitive users in those bands remove them out of the N-person game and assess their optional strategies with the licensed users using the 2-person game approach for coexistence with the licensed users. In the sequel of spectrum sharing, we present three novel priority-based spectrum allocation techniques for enabling dynamic spectrum access (DSA) networks employing non-contiguous orthogonal frequency division multiplexing (NC-OFDM) transmission. The allocation of bandwidth to unlicensed users, without significantly increasing the interference on the existing licensed users, is a challenge for Ultra Wideband (UWB) networks. We propose a novel Rake Optimization and Power Aware Scheduling (ROPAS) architecture for UWB networks as multipath diversity in UWB communication encourages us to use a Rake receiver.
Advisors/Committee Members: Agrawal, Dharma.
Subjects: Computer science
Keywords: Cognitive Radio; Software Defined Radio; Spectrum Sensing; Spectrum Sharing; Game Theory; Hidden Markov Models
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18.
Gieske, Edmund Joseph.
Critical Words Cache Memory.
Degree: PhD, Engineering : Computer Science and Engineering, 2008, University of Cincinnati
► The major constraints on increasing computer performance are power dissipation and memory…
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▼ The major constraints on increasing computer performance are power dissipation and memory latency. These have led to increases in secondary cache memory (L2$) capacity to minimize the occurrence of power intensive and slow off-chip main memory accesses. However as they have grown, secondary cache memories have become a large part of the total processor power dissipation, and their access time has increased in terms of processor clock cycles. Most cache memory architecture research has focused on primary cache memory (L1$) or the overall cache hierarchy. In contrast, architectural improvements of the L2$ have usually been simple increases in capacity and associativity. Our research concerns two previously unexamined attributes of L1$ misses and a novel architectural means to reduce the average hit time and power dissipation of L2$ designs without negatively impacting their hit rates. We investigate both a form of sequence regularity in L1$ miss streams and the quantity of critical words within cache blocks as indicators of the potential for memory hierarchy speed and power improvements resulting from segregating the L2$ treatment of so-called critical and non-critical words. We call the form of sequence regularity "critical word regularity" (CWR), the amount of critical words within cache blocks "critical footprint size" (CFS), and cache memories with architectures that exploit CWR and CFS we call "critical words cache" (CW$) memories. We describe practical CW$ architectures, operating methods, and implementation approaches. We show that CW$ memories offer dramatically higher performance than standard cache architectures employing the well-known critical word first bus protocols. Our investigation consisted of four major phases, each of which employed a trace-driven cache simulation experiment. The goal of the first phase was to determine whether significant CWR exists in the load miss stream of a primary data cache memory (L1D$). Having found this to be the case, initial estimates of potential CW$ performance were made. The second phase sought to quantify the CWR and CFS in the load miss streams of the SPEC CPU 2000 collection of benchmark applications across nine L1D$ configurations. The CWR results of the second experiment were then used to estimate both secondary CW$ coverage of L1D$ load misses and the overall performance of a computer system with a memory hierarchy that includes a CW$. The third phase of our investigation built on the second and more completely measured CWR and CFS. The range of benchmarks was expanded in the third phase experiment and the CWR of instruction fetch misses and data store misses were measured in addition to that of data load misses. The CFS distributions were also measured to better estimate the resource requirements for practical CW$ memories. The fourth and final phase of our investigation determined the workload performance improvements obtainable with practical CW$ memories of various capacities, configurations, operating methods, and implementations. We also further explored the cost and performance tradeoffs made possible by exploitation of CWR and CFS using a CW$ secondary cache architecture. Our investigation shows that sufficient CWR exists in both data and instruction miss streams for the segregation of the critical words in L2$ blocks to be worthwhile. The average CWR for all miss types in both SPEC CPU 2000 and 2006 workloads was found to range from almost 40% up to 90%, across a wide range of L1$ configurations. CWR was found to depend primarily on the workload and secondarily on the cache configuration. We also found that on average, more than half of all cache blocks that are repeatedly missed in a L1$ have only one critical word - even in L1$ designs composed of large, 128 byte, blocks. With one exception, in all of the L1$ configurations we examined only one quarter of the words were ever critical words in more than 77% of the repeatedly missed cache blocks in the data load miss streams. We used our CWR and CFS results to estimate that exploitation of criticality in L1$ miss streams by using a secondary CW$ has the potential to cover more than 60% of L1D$ load misses more quickly and efficiently than standard architecture cache memories. Several practical CW$ configurations were found that achieve average L2$ hit coverage in excess of 70%. CW$ hit coverage was also found to scale well, generally increasing with overall cache capacity. The CW$ architecture offers significant reductions in both L2$ average access time and dynamic power consumption. Our timing, power, and area estimates of practical CW$ memories indicate that the CW$ architecture is more power and area efficient for a small 128KB capacity L2$. However, a small capacity CW$ offers no system level execution time advantage over the standard serial L2$ architecture. In contrast, the CW$ advantages for a large capacity L2$ are profound. For example, compared to an 8MB capacity standard serial access cache memory, a comparable CW$ would be more than 25% faster, while using 76% less energy per hit access, and occupying 62% less area. Another 8MB CW$ configuration would use 40% less energy per hit access, occupy 63% less die area, and be 32% faster, while dissipating only 3% worse leakage power than the comparable standard serial cache memory. If these CW$ memories replaced a standard architecture critical word first 8MB L2$ in a high-performance computer system, the resulting system would respectively be 19% and 22% faster. We also show that secondary CW$ memories provide significant architectural flexibility, enabling smaller, faster, and more power efficient cache memories to be used without degrading overall memory hierarchy performance or efficiency. In turn, smaller and thus lower latency cache memories may enable simpler (e.g., single-threaded, in-order) processor cores to be used. Taken together, all these architectural possibilities would yield significantly more power efficient and higher performance computers for the same cost and fabrication technology.
Advisors/Committee Members: Carter, Harold.
Subjects: Computer science; Electrical engineering; Engineering; Information Systems; Systems design
Keywords: computer architecture; cache memory; critical word; criticality; regularity; critical footprint
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19.
Gilbert, Juan Eugene.
Arthur: An Intelligent Tutoring System with Adaptive Instruction.
Degree: PhD, Engineering : Computer Science and Engineering, 2000, University of Cincinnati
► A novel Web-based intelligent tutoring system, called Arthur, is developed in this…
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▼ A novel Web-based intelligent tutoring system, called Arthur, is developed in this work. This system provides adaptive instruction between various instruction methods that are created by expert tutors. Intelligent tutoring systems are forms of expert systems, where each tutor is an expert in the field and has a different instruction style. Arthur makes use of learning styles theory (Dunn 1978) and mastery learning (Bloom 1976), from education, and case-based reasoning (Kolodner 1993), from artificial intelligence, to bring this new style of asynchronous instruction to the World Wide Web. Case-based reasoning is used to adaptively change instruction methods when corrective instruction is necessary. Unlike the traditional tutoring environment or classroom environment where there is a one-to-one relationship or one-to-many relationshp between the tutor and student or students, Arthur provides a many-to-one relationship between the tutors and student. Imagine taking a course where the student has an unlimited number of tutors available. The purpose of this system is to provide effective instruction via the Web in search of "A Significant Difference" (Russell 1999) in learner outcomes. Chapter 1 gives an introduction to this research. Chapter 2 reviews previous contributions through other Web-based systems that consider learning style as part of their design. Chapter 3 will focus on Arthur's design and explain "What is Arthur?" Chapter 4 discusses the experiment and the experiment results. Finally, Chapter 5 will summarize Arthur and its contributions.
Advisors/Committee Members: Han, Chia Y.
Keywords: Intelligent Tutoring System; Adaptive Instruction; Web-based Instruction
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20.
Govindarajan, Sriram.
Algorithms for Design Space Exploration and High-level Synthesis for Multi-FPGA Reconfigurable Computers.
Degree: PhD, Engineering : Computer Science and Engineering, 2000, University of Cincinnati
► The Reconfigurable Computer (RC) consists of multiple Field Programmable Gate Array (FPGA)…
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▼ The Reconfigurable Computer (RC) consists of multiple Field Programmable Gate Array (FPGA) devices, memory banks and interconnection hardware between the FPGAs. The RC, offering a wide variety of hardware resources but limited in quantity, poses a challenge to design automation techniques. The state-of-the-art design automation for RCs direly requires efficient High-Level Synthesis (HLS) and behavioral partitioning techniques that can effectively utilize the rich set of resources. The spatial and temporal (behavioral) partitioning techniques for RCs rely heavily on HLS to provide high-level estimates and a sound back-end support for synthesizing the partitioned designs. Thus, HLS plays a central role in the design automation of RCs. HLS comprises of a collection of well-established sub-problems, each of which are known to be NP-complete. HLS techniques have gained popularity primarily due to their ability to quickly explore a wide variety of structural implementations, for a given behavioral specification of the design. However, there is an ever increasing need for HLS techniques that satisfy application specific requirements and utilize target-architecture-specific features to perform efficient high-level exploration and synthesis. This thesis presents a high-level synthesis framework consisting of a variety of HLS techniques and models that collectively provide complete synthesis support for the design automation of RCs. Traditional interaction between HLS and spatial partitioning is primarily to obtain a quick estimate on a contemplated solution, using a naive exploration model. This kind of an interaction is inadequate because high-level exploration is performed without any knowledge about the partitioned configuration of the behavior. This thesis presents a novel exploration technique that incorporates a partitioning-based exploration model. The exploration model, unlike traditional HLS exploration model, views a four-dimensional design space consisting of multiple spatially partitioned segments of the behavior. The exploration technique has the ability to simultaneously explore the design space of all partitioned behavior segments and generate multiple structural implementations, one for each FPGA device on the RC. In order to provide close interaction between synthesis and partitioning, we provide an exploration framework that can be integrated with any partitioning algorithm. The exploration framework provides an collection of methods that a partitioner can use to control the trade-off between time spent in exploration and the amount of design space explored. The framework can be used by a partitioner to either dynamically perform exploration or statically generate design points prior to partitioning. In addition, the framework incorporates behavioral exploration at two levels of abstraction: the block-level BBIF specification that represents a single thread of control, and the task-level USM specification that represents multiple threads of control. Traditional HLS developed for ASICs are not quite suitable for RCs that provide a limited set of resources. This thesis presents two new techniques that efficiently utilize the resources on the RC architecture. We have developed a application-specific macro-based synthesis process that dynamically generates macro components specific to an application and uses these during HLS. This technique results in considerable improvement in the design performance for RCs. We also developed an improved register optimization and binding technique that results in considerable reduction in the design area on the RC. The scheduling phase of HLS forms an integral part of the exploration and synthesis process since it directly impacts the area-speed tradeoffs of the design. This thesis presents three scheduling techniques that are used during high-level synthesis and exploration. This thesis presents a new time-constrained scheduling algorithm that has low-complexity, yet produces good quality schedules. This scheduling algorithm is an ideal candidate for high-level exploration with partitioning since millions of solutions will have to be evaluated. Moreover, since the algorithm is time-constrained, it enables the exploration framework to handle a latency constraint on the given behavior. The scheduling algorithm and a collection of HLS estimation algorithms have been integrated with exploration framework. The high-level synthesis system incorporates the widely used resource-constrained Force Directed List Scheduling (FDLS) Algorithm developed by Paulin and Knight. We have developed an improved FDLS technique that significantly reduces the computational intensity of the original FDLS algorithm without degrading the schedule quality. Even a small improvement in the schedule quality translates to a significant increase the design throughput. Finally, this thesis presents another resource-constrained cone-based list scheduling algorithm which generates better quality schedules than FDLS at the expense of little computational overhead, for a class of DSP applications.
Advisors/Committee Members: Vemuri, Ranga R.
Keywords: synthesis; partitioning; exploration; reconfigurable computing; design automation
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21.
HANDA, MANISH.
ONLINE PLACEMENT AND SCHEDULING ALGORITHMS AND METHODOLOGIES FOR RECONFIGURABLE COMPUTING SYSTEMS.
Degree: PhD, Engineering : Computer Science and Engineering, 2004, University of Cincinnati
► An operating system is required for controlling the applications and managing the…
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▼ An operating system is required for controlling the applications and managing the FPGA resources in a multi-user multi-tasking reconfigurable computing platform. In our research, we examine computer aided design (CAD) issues involved in the design of a reconfigurable operating system (ROS). In our model of the reconfigurable operating system, a host is responsible for managing reconfigurable resources and execution of applications. Main CAD operations performed by the the host include temporal partitioning, synthesis, online scheduling and online placement. We present an efficient algorithm for finding empty area on the FPGA as a list of maximal empty rectangles. In addition to being fast, our algorithm handles dynamic addition and deletion of tasks efficiently while maintaining a high quality placement. We use bin packing heuristics for choosing suitable placement location for a task. We provide detailed characteristics of the online placement system. We present an integrated online scheduling and placement methodology. We defer scheduling decisions until it is absolutely necessary to accommodate dynamically changing task priorities. We show by experimentation that in-order task execution strategy guarantees the shortest execution time and the the out-of-order strategy results in better FPGA area utilization. We use computational geometry algorithms and data-structures for placement of rectilinear tasks. Our algorithm can be used for placement of mixed rectangular and rectilinear tasks. We propose a run-time efficient algorithm to quantify the amount of fragmentation of area resources in a given rectangular bounding box area on the FPGA. We demonstrate that fragmentation aware online placement results in better placement quality. Massive parallelism inherent in a hardware implementation of an algorithm can be explored for its faster execution as compared to its software implementation. We present three different reconfigurable architectures for two dimensional online placement. Each architecture makes different trade-offs between execution time, area usage, memory requirement and reconfiguration overheads. Shifting of task placement and scheduling responsibility to hardware reduce the time tick processing overhead and result in faster placement and scheduling decisions. We propose a hardware based integrated online placement and scheduling algorithm.
Advisors/Committee Members: Vemuri, Dr. Ranga.
Keywords: Integrated Circuits, Computer Aided Design, Field Programmable Gate Arrays, FPGA, Reconfigurable Computing, Online Placement and Scheduling
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22.
Hauser, James William.
Approximation of Nonlinear Functions for Fixed-Point and ASIC Applications Using a Genetic Algorithm.
Degree: PhD, Engineering : Computer Science and Engineering, 2001, University of Cincinnati
► This research addresses the problem of efficient function approximation for systems-on-a-chip. In…
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▼ This research addresses the problem of efficient function approximation for systems-on-a-chip. In these systems, high speed, minimal chip size, and efficient computation are necessary. Examples include computing temperature using a thermistor and evaluating trigonometric functions. For function approximation, system engineers commonly use an off-the-shelf package to generate an approximating polynomial from a set of sampled data. The floating-point coefficients are rounded to integer values that match the target architecture's size. The induced rounding errors can actually be due to this solution space translation. To minimize or eliminate the rounding effect, the optimal coefficient set should be found using the restricted target's integer space. This is an integer programming problem, which is NP-hard. To find the optimal coefficients, the restricted target space can be enumerated, but this takes an excessive amount of processing time. Alternatively, a heuristic such as a genetic algorithm can be used to find a feasible solution. In this research, a genetic algorithm is devised to find a set of polynomials, with integer coefficients, that in a piecewise fashion minimizes the sum-of-squared error over a set of experimentally gathered or function sampled data.
Advisors/Committee Members: Purdy, Dr. Carla.
Keywords: genetic algorithm; integer coefficients; piecewise polynomial; curve fitting; fixed point
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23.
He, Bing.
Architecture Design and Performance Optimization of Wireless Mesh Networks.
Degree: PhD, Engineering : Computer Science and Engineering, 2010, University of Cincinnati
► Wireless Mesh Network (WMN) is a promising wireless technology in providing high-bandwidth…
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▼ Wireless Mesh Network (WMN) is a promising wireless technology in providing high-bandwidth Internet access over a specific coverage area, with relative lower investment cost as compared to traditional access network. In a WMN, a mobile client (MC) can access the Internet through a wireless backbone formed by wireless Mesh Routers (MRs) which are interconnected in a multi-hop fashion while some MRs known as Internet Gateways (IGWs) act as the communication bridges between the wireless backbone and the Internet. The design of the network architecture is a fundamental issue for a WMN and is critical in determining the network performance and providing Quality of Service (QoS) for end users, and thus should be addressed carefully. A unique characteristic of a WMN is the IGW oriented Internet traffic. Thus, the deployment of IGW is the key problem in the network design, and is investigated in this dissertation. Two IGW oriented network architecture are analyzed, and corresponding QoS requirements and constraints are evaluated. The IGW deployment problem is then formulated as a multiple objectives optimization problem. Besides the linear program approach, some heuristic algorithms are proposed and evaluated. Extensive simulations show the effectiveness of proposed solutions. To improve the performance of a given WMN, load balancing between different IGW domains is also investigated. A fairness between IGWs domains improves the network performance and provides a better QoS for end users. The fairness index is defined for both homogenous and heterogeneous WMNs. A distributed load balancing scheme is proposed, and three load balancing algorithms based on diffusion methodology are introduced in the proposed scheme. Authenticated key establishment (AKE) schemes enable two entities (e.g., a client and a server) to share common communication keys in an authentic way. Due to mobility of mesh clients (MCs), a WMN needs have a fast and efficient authentication and key establishment scheme to provide adequate security in client's handoff while meeting the Quality of Service (QoS) requirements. In this dissertation, we discuss the authentication performance requirements imposed by the unique WMN characteristics. Distributed authenticated key establishment schemes are proposed based on hierarchical multi-variable symmetric functions (HMSF) and identity-based cryptography (IBC) respectively, which enable fast key agreement and mutual authentication between network entities in a WMN. In the distributed authenticated key establishment scheme, network entities in a WMN such as MCs and mesh access points (e.g. mesh routers) can authenticate each other and establish pairwise communication keys without any interaction from a centralized authentication center, while substantially reducing the communication overhead and the authentication delay.
Advisors/Committee Members: Agrawal, Dharma.
Subjects: Computer science
Keywords: Wireless Mesh Networks; Internet Gateway; Load Balancing; Authenticated Key Establishment; Symmetric Polynomial; Identity-based Cryptography
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24.
HELMICK, MICHAEL T.
EFFICIENT GROUP COMMUNICATION AND THE DEGREE-BOUNDED SHORTEST PATH PROBLEM.
Degree: PhD, Engineering : Computer Science and Engineering, 2007, University of Cincinnati
► In this thesis we develop a framework for studying and understanding the…
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▼ In this thesis we develop a framework for studying and understanding the tradeoffs involved in efficient multicast route determination. Using this framework, we developed an algorithm (Myriad) that exhibits superior theoretical and empirical results over previously published work. We have validated this work through extensive simulation using a variety of metric spaces, and by proving a series of mathematical theorems concerning degree-bounded spanning trees over metric spaces. This study is done through examination of the degree-constrained minimum average-latency spanning tree problem (or DC-MAL). Creating a solution which places each participant at their optimal locality along a path from the root is an NP-hard problem, thus motivating a search for approximate solutions. This type of organization for information relaying is a natural model of the multicast problem and lends itself to theoretical analysis that can be applied in application level peer-to-peer overlay networks. Out-degree constraints follow directly from the need for high bandwidth multimedia streams and the ability to relay the information without any loss. Study of this problem is important since it is expected that the demand for multicast applications will continue to grow, and such applications require scalability to millions of simultaneous subscribers.
Advisors/Committee Members: Annexstein, Dr. Fred S.
Subjects: Computer Science
Keywords: multicast, degree-bounded, shortest path, graph theory, Myriad
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25.
HUANG, RENQIU.
PHYSICAL AWARE HIGH LEVEL SYNTHESIS AND INTERCONNECT FOR FPGAs.
Degree: PhD, Engineering : Computer Science and Engineering, 2006, University of Cincinnati
► Reconfigurable computing (RC) is going mainstream where FPGA plays an essential role.…
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▼ Reconfigurable computing (RC) is going mainstream where FPGA plays an essential role. Synthesizing the application from concept and prototyping onto reconfigurable FPGAs has emerged as one of the main challenges in design automation area. A large number of new applications show the huge potentials of synthesis strategy and architecture development for FPGAs. The work presented in this dissertation deals with the synthesis and novel architecture of FPGAs. In particular, it tries to address physical aware high level synthesis (PAHLS) methodology to ensure the synthesis integrity for FPGAs. Motivated by the study of PAHLS, a hybrid interconnect structure is proposed to increase the performance and reconfigurability for FPGAs or FPGA-like reconfigurable platforms. We first present a performance-driven PAHLS where relational placement is combined with the macro generation strategy during high level synthesis. Second, we present an automated framework to integrate physical placement information into high-level synthesis that is believed to be the first on-line synthesis methodology for partially reconfigurable FPGAs. The presented synthesizer allocates the FPGA resources adaptively and is incremental in nature. The algorithm is designed to be linear in terms of the number of operations to ensure its on-line usage. We then present a transformation mechanism to extend the synthesis frontier to heterogeneous configurable architectures. We develop an automatic synthesis methodology which attacks both memory and logic assignments by interacting with behavioral synthesis. Next, we present a hybrid interconnect structure which takes advantages of both mesh and tree interconnect topologies. The presented architecture is investigated with a combinatorial analysis which examines the number of switches needed. Our evaluation demonstrates that the presented model has less switch accrued effects due to the introduction of tree networks. Finally we extend that hybrid interconnect structure to support multi-granular configuration. We also develop a fast evaluation tool to simulate on-line placement and routing effects by applying that interconnect on a run-time reconfigurable platform. The studies show the efficiency of the extended model in overcoming the fragmentation problem with a penalty of modest increase in the number of switches for the construction of that interconnect.
Advisors/Committee Members: Vemuri, Dr. Ranga.
Subjects: Computer Science
Keywords: High level synthesis, system synthesis, algorithm, architecture, performance, interconnect, analysis, evaluation
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26.
JAIN, NEHA.
ENERGY AWARE AND ADAPTIVE ROUTING PROTOCOLS IN WIRELESS SENSOR NETWORKS.
Degree: PhD, Engineering : Computer Science and Engineering, 2004, University of Cincinnati
► Recent technological advances have enabled distributed micro-sensing for large scale information gathering…
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▼ Recent technological advances have enabled distributed micro-sensing for large scale information gathering through a network of tiny, low power devices or nodes equipped with programmable computing, multiple sensing and communication capabilities. This network of sensor nodes, known as a wireless sensor network, has revolutionized remote monitoring applications because of its ease of deployment, ad hoc connectivity and cost-effectiveness. In this dissertation, we design distributed routing protocols for minimizing energy consumption in a sensor network. There are two main contributions of this work. The first contribution is the design of an energy aware multiple path routing protocol to route heavy data traffic between a source and a destination node in a sensor network. The protocol spreads the routing load between the source and destination nodes over a large number of sensor nodes to minimize disparity in the energy levels of the sensor nodes. We also grade the multiple paths based on their route length to support time critical queries on the shortest available paths. The second contribution is the design of a communication architecture that supports distributed query processing to evaluate spatio-temporal queries within the network. We represent these queries by query trees and distribute query operators to appropriate sensor nodes. As operator execution demands high computation capability, we propose use of a heterogenous sensor network where query operators are assigned to sparsely deployed resource-rich nodes within a dense network of low power sensor nodes. We design an adaptive, decentralized, low communication overhead algorithm to determine an operator placement on the resource-rich nodes in the network to minimize cost of transmitting data in the routing tree constructed to continuously retrieve data from a set of spatially distributed geographical regions to the sink. To the best of our knowledge, this is the first attempt to build an energy aware routing infrastructure to enable in-network processing of spatio-temporal queries. In order to maximize energy savings the proposed multiple path routing protocol can be used to route data between the nodes that form the routing tree.
Advisors/Committee Members: Agrawal, Dr. Dharma P.
Subjects: Computer Science
Keywords: Wireless Sensor Networks, Routing Protocols, Energy Aware, Decentralized algorithms
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27.
JAIN, NITIN.
MULTICHANNEL CSMA PROTOCOLS FOR AD HOC NETWORKS.
Degree: MS, Engineering : Computer Science and Engineering, 2001, University of Cincinnati
► An ad hoc network is a collection of wireless mobile nodes dynamically…
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▼ An ad hoc network is a collection of wireless mobile nodes dynamically forming a network without the use of any existing stationary network infrastructure. The network can be multi-hop and mobile; there is no central controller and packet transmissions are typically unsynchronized. The efficiency of the medium access control (MAC) protocol to coordinate the access to the shared radio medium is critical. Carrier sense multiple access (CSMA) protocols are typically used. However, their efficiency is limited when the load and the level of contention is high. This thesis proposes use of multichannel CSMA protocols to reduce contention on the wireless medium. Though the aggregate capacity with a multichannel scheme is the same as a single channel, contention per channel is now lower and thus channel access is more efficient. We show that only a handful of channels provide optimum performance as with too many channels per-channel bandwidth is too low that affects performance adversely. Since the number of channels are much lower than the number of nodes, effective channel selection schemes are needed. We propose a receiver-based channel selection (RBCS) scheme that selects channel based on interference levels on different channels at the receiver. We implement this technique as an extension of IEEE standard 802.11 MAC protocol (which is a single channel protocol) on a network simulator. We show that it provides superior delay performance at high loads compared to single channel, as well as other, previously studied, channel selection schemes, such as selcting a random free channel or selecting channel based on sender-side signal power. As a final contribution, we study the effect of multichannel CSMA protocols for multipath routing on ad hoc networks. With use of single channel CSMA, ''route coupling'' can exist for multipath routes. This means that routes can form in radio neighborhood, and their transmissions can interfere with each other, preventing multiple routes to be used concurrently. Thus, the load balancing advantages of multiple paths are lost. We show that the use of multichannel CSMA protocols as above can remarkably improve the effectiveness of the multipath routing by providing more diversity.
Advisors/Committee Members: Das, Dr. Samir R.
Subjects: Computer Science
Keywords: Ad Hoc Networks; medium access control; multichannel MAC; wireless networks; channel selection techniques
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28.
JAIN, VIVEK.
ON-DEMAND MEDIUM ACCESS IN HETEROGENEOUS MULTIHOP WIRELESS NETWORKS.
Degree: PhD, Engineering : Computer Science and Engineering, 2007, University of Cincinnati
► Recent years have witnessed an extensive proliferation of wireless technology in every…
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▼ Recent years have witnessed an extensive proliferation of wireless technology in every domain of day-to-day life. Examples include mobile phones, broadband communication, wireless LAN, wireless enabled PDAs, cordless phones, garage-door openers and the list continues. Advancements in radio technology, antenna technology, low power computational digital signal processing (DSP) and micro-electro-mechanical systems (MEMS) are instrumental in reducing the size and cost of wireless devices. A wireless network consists of wireless devices forming an infrastructure-based or a peer-to-peer network. A network can be a single-hop or multihop network. Single-hop networks are already in existence and have been substantially investigated. This dissertation thus focuses on multihop wrireless networks, where the intermediate wireless devices also act as routers. Depending on their functionality, multihop wireless networks can be categorized into ad hoc, mesh and sensor networks. A mobile ad hoc network (MANET) aims at provding a mobile network with connectivity similar to a wired network without the need for any infrastructure support. A wireless mesh network (WMN) typically extends the infrastructure based single hop wireless network and has become a new paradigm for providing last mile broadband access. A wireless sensor network (WSN) is similar to an ad hoc network, providing a cheap alternative to monitoring applications. Each of these multihop wireless networks has their own set of challenges with respect to operation and implementation. The first part of this dissertation focuses on developing on-demand medium access control (MAC) protocols for multiple beam smart antennas (MBSAs) in ad hoc and mesh environments. MBSA has the unique capability of simultaneously initiating packet transmissions or receptions in multiple beams. Thus, compared to traditional omnidirectional antennas, MBSA can better utilize the spatial bandwidth, thereby increasing the capacity of wireless networks. We have performed both simulation and analytical studies to evaluate the proposed protocols for MBSA in ad hoc environments. To the best of our knowledge, this is the first attempt to analyze and develop on-demand protocols for multiple beam smart antennas. We have also proposed a cost-effective mesh network architecture employing heterogeneous antenna technologies and hybrid MAC protocol. The second part of this dissertation focuses on designing energy-efficient and reliable medium access mechanisms for wireless sensor networks. Sensor motes are battery-operated, hence protocols designed for them have to be innately energy-efficient. Also, depending on the application, reliability and latency might be important parameters. Taking into account all these design considerations, we have proposed dual-radio architecture. A low-energy wakeup radio is used to transmit and receive wakeup tones, while another transceiver is used for data communication. We have demonstrated the superior performance of our protocol using extensive simulation and analytical studies. We have also proposed a wireless sensor network testbed for quantifying reliability of wireless channels. The setup can be used to quantify reliability of wireless channels in terms of packet error rate, received signal strength and overall latency of the system. On the basis of our studies, we have provided deployment guidelines and medium access strategies for wireless sensor networks.
Advisors/Committee Members: Agrawal, Dr. Dharma P.
Subjects: Computer Science
Keywords: Ad hoc Network, Concurrent Packet Reception, Deafness, Differentiated Service Classes, Medium Access Control, Mesh Network, Multihop Wireless Network, Multiple Beam Smart Antenna, Sensor Network
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29.
Joshi, Avinash.
Load Balancing, Queueing and Scheduling Mechanisms in Mobile Ad Hoc Networks.
Degree: MS, Engineering : Computer Science and Engineering, 2001, University of Cincinnati
► An ad hoc network is a collection of mobile nodes with wireless…
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▼ An ad hoc network is a collection of mobile nodes with wireless links that dynamically form a network without the use of any existing network infrastructure or centralized administration. Due to the limited range of the wireless links, multiple network “hops” may be needed for one node to exchange data with another across the network. In recent years, a variety of new routing protocols targeted specifically at this environment has been developed. It is our thesis that capacity of wireless networks being limited, routing performance is heavily influenced by congestion, load imbalance, scheduling priorities and wireless link quality. Our work focuses on developing techniques to address these issues. The overall goal is improved overall routing performance. The following techniques have been studied in connection with on-demand routing protocols, specifically AODV (ad hoc on-demand distance vector routing). Typically, routing protocols discover shortest path route based on number of hops. This routing philosophy can lead to bottlenecks as some links tend to be used by many routes. We present techniques which try to balance the load and avoid such bottlenecks. We use a new routing cost metric which is a function of the current load on each node on a route. The idea of the cost metric is to be able to route around the nodes that are congested for which alternate routes are available. In addition, rerouting is done proactively when any node on an active route starts getting congested. We also investigate efficient queueing paradigms to be used at the radio interfaces for nodes in wireless ad hoc networks. Low bandwidth of wireless links makes queueing paradigms critical for the performance of the network routing protocol. We investigate various packet drop and priority scheduling policies. We demonstrate that effective queueing paradigms can improve routing performance. Unlike wired networks, packets transmitted on wireless channels are often subject to burst errors which cause back to back packet losses. Most link layer protocols recover from packet losses by retransmission. When the wireless channel is in a burst error state, retransmission attempts typically fail, thereby causing poor utilization of the wireless channel. We investigate a channel state dependent scheduling policy where packets are scheduled at the radio interface based on the link quality. Packets seeing a better link quality get higher priority. Conversely, packets seeing weak links are buffered to be transmitted later. We show this technique improves overall channel utilization which in turns improves routing performance.
Advisors/Committee Members: Das, Dr. Samir R.
Subjects: Computer Science
Keywords: Mobile Ad Hoc Networks; dropping policies; scheduling policies
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30.
JOSHI, TARUN.
CROSS LAYER OPTIMIZATIONS FOR PERFORMANCE ENHANCEMENT OF WIRELESS NETWORKS.
Degree: PhD, Engineering : Computer Science and Engineering, 2006, University of Cincinnati
► In this dissertation, we focus on designing several cross-layer optimizations to boost…
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▼ In this dissertation, we focus on designing several cross-layer optimizations to boost the performance of wireless networks. We categorize our efforts into two directions: (a) improvement of spatial reusability and multi-hop performance via Directional Antennas, and (b) analysis and optimization of the IEEE 802.11 multi-rate networks. Since existing protocols are incapable of fully exploiting the benefits of a directional antenna system, we propose a, broadcast and routing protocol for such systems. All our proposals assume cross layer interaction between the Network, MAC and PHY layers. Next, we analyze multi-rate networks in the context of IEEE 802.11 DCF networks and propose an analytical model to study the link-delay characteristics of such systems. We then propose an online algorithm Time Fair CSMA (TFCSMA), for guaranteeing air-time fairness and thereby mitigating the recently observed rate anomaly problem of IEEE DCF multi-rate networks. Following the design of TFCSMA, we concentrate on the problem of rate adaptation for time-varying wireless channels. We thoroughly investigate the impact of transmission rate on the performance of a wireless link. We then propose Stochastic Automata Rate Adaptation Algorithm (SARA). SARA is inspired by Stochastic Learning Automata (SLA), a machine learning technique for adaptation in random environments. As opposed to the previous work in this area, SARA is ideally suited for both stationary and non-stationary channel environments and is completely compatible with the existing IEEE 802.11 MAC standard.
Advisors/Committee Members: Agrawal, Dharma.
Keywords: Wireless; 802.11
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