Department: Engineering : Computer Engineering ![[clear]](close-x.png "Remove this limiter")
207 matches in the database.
These are records: 1 - 30.
Did you mean instcode:ucii?
[1] [2] [3] [4] [5] [6] [7]
1.
ABDEL-MOMEN, SHERIF SAMIR.
DYNAMIC RESOURCE BALANCING BETWEEN TWO COUPLED SIMULATIONS.
Degree: MS, Engineering : Computer Engineering, 2003, University of Cincinnati
► Coupled simulations form an important class of simulations that involve the concurrent…
(more)
▼ Coupled simulations form an important class of simulations that involve the concurrent execution of two (or more) different simulations. A bottleneck is created at synchronization points when one simulation has to wait idle for the other simulation. This scenario appears when the processors are statically distributed between the coupled simulations, not taking into consideration the dynamic change of the workload of each coupled simulations. As the difference between the workloads of the coupled simulation increases, the idle time also increases because the simulation with the larger workload spends more time in computation while the other simulation is waiting for synchronization. Dynamic resource balancing is the solution that we developed to overcome the problem of wasted idle time. We use the dynamic creation and deletion of processes provided by MPI-2 to rebalance the coupled simulation. Our results showed a reduction in waiting time and an improvement in the overall system performance.
Advisors/Committee Members: Tomko, Dr. Karen.
Subjects: Computer Science
Keywords: coupled simulation; load balancing; network of workstations; parallel simulations; process creation
More Like This
2.
AGARWAL, NEETU.
ON FORMAL DEVELOPMENT OF ANALOG/DIGITAL INTERFACES IN MIXED-SIGNAL CIRCUITS.
Degree: MS, Engineering : Computer Engineering, 2005, University of Cincinnati
► The trend of integrating complete analog/digital systems on a single chip has…
(more)
▼ The trend of integrating complete analog/digital systems on a single chip has resulted in new challenges in modeling and simulation. First of all, problems in analyzing these circuits arise due to the different modeling and simulation approaches used for analog and digital circuits, and differences in their accuracy requirements. Secondly, to cope with the complexities of large designs, systems level behavioral modeling and simulation are essential to the validation of a proposed architecture before a detailed design begins. This has been used in digital system design for many years with success. Designs are described and simulated at the behavioral level using standard hardware description languages. In the analog domain, circuits were mostly designed and verified at the electrical level. This kind of circuit simulation is time-consuming and not practical for large and complex circuits. For mixed-signal simulation, it is essential to provide an analog modeling and simulation environment similar to the digital domain, which would allow the designer to model components at behavioral level and then perform systemlevel analog simulation. Various hardware description languages, such as VHDL-AMS and Verilog-A have been developed as mixed-signal hardware description languages. In this thesis, we analyze various constructs in VHDL-AMS for modeling analog/digital interfaces and propose algorithms and new semantic constructs to reduce the time delay at the analog/digital interface in VHDL-AMS mixed-signal models.
Advisors/Committee Members: Carter, Dr. Harold W.
More Like This
3.
AGRAWAL, SHISHIR.
OPTIMIZATION APPROACHES FOR ANALOG KERNEL TO SPEEDUP VHDL-AMS SIMULATION.
Degree: MS, Engineering : Computer Engineering, 2002, University of Cincinnati
► The dynamic behaviour of physical systems exhibit both continuous and discrete behavior.…
(more)
▼ The dynamic behaviour of physical systems exhibit both continuous and discrete behavior. The discrete behavior can be described using discrete-event models. Differential and algebraic equations (DAEs) are used to specify continous behaviour. Traditionally, languages like VHDL and Verilog have been used to model and simulate discrete event models whereas languages like SPICE and SPECTRE have been used to model continuous systems. There was a clear gap between simulating designs with digital and analog components together. This gap has been now filled by mixed-signal languages like Verilog-AMS and VHDL-AMS. However, a major issue in mixed-signal simulation is their performance. Mixed-signal simulators have both a digital kernel and a analog kernel. These two kernels are synchronized to handle interactions between digital and analog kernels. The digital kernel is event-driven and is therefore quite fast, whereas the analog kernel solves a system of ordinary differential algebraic equations (ODAEs) over time and is relatively slow. Thus, the analog kernel is a bottleneck in mixed-signal simulation. To improve the speed of mixed-signal simulation,it is necessary to look at approaches to speed up analog kernel. An analog kernel consists of two phases: 1) a matrix build phase ( in which all the equations at the current time are loaded into the matrix ) and 2) a solution phase ( in which the matrix is solved ). Prior research has been focussed on improving the solution phase as matrix solution time is O(n 3 ), where n is the number of equations. However, we cannot neglect the matrix build phase, which can take as much as 50-70% of the total simulation time as the circuit size increases. This research has been focused on investigating optimization approaches to reduce the time taken in the matrix build phase. We propose three approaches that result in a reduction in time taken during the matrix build phase and therefore in the total simulation time as well. These methods when combined together show a typical improvement of 40-50% for the models we investigated in this thesis.
Advisors/Committee Members: Carter, Dr. Harold W.
Keywords: mixed-signal simulation; VHDL-AMS; analog kernel; optimizations for matrix build phase
More Like This
4.
Alla, Ravi Chandar.
Design and Implementation of an analog to digital conversion mechanism for an in-situ monitoring microelectrode SOC.
Degree: MS, Engineering : Computer Engineering, 2008, University of Cincinnati
► A lot of importance has been given to the problem of addressing…
(more)
▼ A lot of importance has been given to the problem of addressing the direct and indirect causes of the environmental pollution. Developing methods to effectively monitor and control pollution in the environment has been a major research area in recent years. Many sites containing toxic chemical spills and other waste materials from industries require constant and long term monitoring to reduce the detrimental impacts on public health.In-situ monitoring has gained a lot of importance and has become the most cost-effective and reliable way of monitoring the concentration of various toxicants. A system consisting of the microelectrode sensors with data-processing circuitry for analyzing the sample data at the remote user is essential for in-situ monitoring. This thesis work explains the development of an efficient analog to digital conversion mechanism for a second generation micro electrode SOC. This thesis work presents an efficient approach of the design of ADC for getting high resolution, low power and to consume less silicon area. The design has been fabricated in AMI 0.5 µ m process at MOSIS fabrication facility. Results of the post silicon testing of the system and the ADC have been reported and the system is analyzed for performance. The results show that the analog to digital conversion mechanism designed can be used in the microelectrode SOC for in-situ environmental monitoring from 0.6 to 4.5 V providing 16 bit resolution.
Advisors/Committee Members: Beyette, Fred.
Subjects: Engineering
Keywords: ADC; Comparator; Current Mirror; Capacitor; voltage; Ramp generator; input voltage
More Like This
5.
ANAND, KUMAR.
A SCALABLE EXPLICIT MULTICAST PROTOCOL FOR MOBILE AD HOC NETWORKS.
Degree: MS, Engineering : Computer Engineering, 2004, University of Cincinnati
► Multicast applications are becoming increasingly important in Mobile Ad hoc Networks (MANETs)…
(more)
▼ Multicast applications are becoming increasingly important in Mobile Ad hoc Networks (MANETs) due to proliferation in group oriented computing. Due to dynamic topology of MANETs, stateless multicast protocols are finding increased acceptance since they do not require maintenance of state information at intermediate nodes. Recently, several multicast schemes have been proposed which scale better with the number of multicast sessions than traditional multicast strategies. These schemes are also known as Explicit Multicast (Xcast; explicit list of destinations in the packet header) or Small Group Multicast (SGM). In this Thesis work, we propose a new scheme for small group multicast in MANETs named Extended Explicit Multicast (E2M), which is implemented on top of Xcast and introduces mechanisms to make it scalable with number of group members for a given multicast session. Unlike other schemes, E2M does not make any assumptions related to network topology or node location. It is based on the novel concept of dynamic selection of Xcast Forwarders (XFs) between a source and its potential destinations. The XF selection is based on group membership and the processing overhead involved in supporting the Xcast protocol at a given node. If the number of members in a given session is small, E2M behaves just like the basic Xcast scheme with no intermediate XFs. As group membership increases, nodes may dynamically decide to become an XF. This scheme, which can work with few E2M aware nodes in the network, provides the transparency of stateless multicast, reduces header processing overhead, minimizes Xcast control traffic and makes Xcast scalable with the number of group members.
Advisors/Committee Members: Agrawal, Dr. Dharma P.
Keywords: Multicast, Explicit Multicast, Wireless Ad Hoc Networks, Small Group Multicast
More Like This
6.
AROLE, ALUKAYODE.
POWER PROFILING: AN INCREMENTAL POWER ANALYSIS TECHNIQUE FOR FPGA-BASED DESIGNS.
Degree: MS, Engineering : Computer Engineering, 2006, University of Cincinnati
► FPGA devices have gradually become a favorable architecture. Their increased chip density…
(more)
▼ FPGA devices have gradually become a favorable architecture. Their increased chip density allows users to develop larger designs that target high clock frequency. As a result of this, FPGA devices are favored for portable, battery-powered applications. However, these reconfigurable devices tend to be more power inefficient compared to ASICs. This drives the need for efficient design techniques and detailed power analysis methods. This thesis will introduce an alternate approach for power analysis called Power Profiling. The process will first be used to identify power consumption per module in a hierarchical architecture. Then using the concept of incremental synthesis, the process will be used to incrementally re-implement the complete design without modifying the implementation of unchanged portions of the design. This way, a designer can iterate implementations towards power efficiency on a specific module without affecting the performance of other modules.
Advisors/Committee Members: Tomko, Dr. Karen A.
Subjects: Black Studies
More Like This
7.
ARORA, VIKRAM.
AN EFFICIENT BUILT-IN SELF-DIAGNOSTIC METHOD FOR NON-TRADITIONAL FAULTS OF EMBEDDED MEMORY ARRAYS.
Degree: MS, Engineering : Computer Engineering, 2002, University of Cincinnati
► With improvements in VLSI technology, more and more components are fabricated onto…
(more)
▼ With improvements in VLSI technology, more and more components are fabricated onto a single chip. The importance of system on chip (SoC) is growing rapidly in this era. It is estimated that the percentage of chip area occupied by embedded memory arrays on a SoC will rise to as high as 94% in the next decade. Even worse, memory arrays are more vulnerable to fabrication defects due to the higher packing density of transistors. If some cells of the embedded memory arrays on a SoC are defective, it is not economical to throw the chip away. The solution to this problem lies in designing an intelligent piece of built-in hardware which tests, diagnoses, and repairs the faulty cells of embedded memory arrays. In this thesis, we propose a built-in self-diagnostic march-based algorithm which identifies memory cells as faulty based on a recently introduced non-traditional fault model. This algorithm is developed based on the DiagRSMarch algorithm which is a diagnosis algorithm for embedded memory arrays for identifying traditional faults in memories. A minimal set of additional operations is added to DiagRSMarch for identifying the non-traditional faults without affecting the diagnostic coverage of the traditional faults. The embedded memory arrays are accessed using the bi-directional serial interfacing architecture which minimizes the routing overhead introduced by the diagnosis hardware. Using the concepts of serial interfacing technique, parallel testing and redundant-tolerant operations, the diagnosis process is accomplished efficiently at-speed with minimal hardware overhead. An implementation of the diagnosis algorithm is achieved in the form of a built-in self-diagnosis (BISD) controller with the memory arrays and their associated interfaces. The BISD Controller interacts closely with the built-in self-repair logic via suitable control signals. Ideally, we expect to have a single controller performing built-in self-test, built-in self-diagnosis and built-in self-repair after the SoC chips are fabricated or during power-on for the SoC chips used for a system. This thesis is a step in meeting this goal.
Advisors/Committee Members: Jone, Dr. Wen-Ben.
Keywords: memory; diagnosis; built-in-self-diagnosis; system on chip; embedded memory arrays
More Like This
8.
ARUMUGAM, THIAGARAJAN.
A heuristic approach for Capacitive Crosstalk Avoidance during Post Global Routing Crosstalk Synthesis for Deep Submicron Technologies.
Degree: MS, Engineering : Computer Engineering, 2008, University of Cincinnati
► With decreasing feature sizes, higher clock rates and increasing interconnect densities, crosstalk…
(more)
▼ With decreasing feature sizes, higher clock rates and increasing interconnect densities, crosstalk has become a major concern in Integrated Circuit (IC) design [1]. Crosstalk optimization is usually performed during placement, global routing and detailed routing. In order to achieve accuracy and flexibility, previous approaches proposed an intermediate step between global routing and detailed routing to perform the crosstalk synthesis. In this work, we present techniques to improve upon the existing capacitive crosstalk aware router developed in [2] which uses a post global routing crosstalk synthesis step to perform crosstalk estimation and reduction. We propose a new approach to automate the process of identifying the amount of crosstalk sensitivity between the nets. Our objective function (noise margin) also significantly reduces the computation time. Finally, we arrive at a crosstalk-free net order for each region of the chip which serves as a good starting point for a detailed router.
Advisors/Committee Members: Carter, Dr. Harold W.
Keywords: Crosstalk, Global Routing, Signal Integrity
More Like This
9.
BADAM, SRINIVAS.
AN IMPROVED EKV TRANSISTOR MODEL WITH DEEP SUBMICRON EFFECTS MODELED IN VHDL-AMS.
Degree: MS, Engineering : Computer Engineering, 2007, University of Cincinnati
► With rising transistor densities and shrinking feature sizes, digital, analog and mixed-…
(more)
▼ With rising transistor densities and shrinking feature sizes, digital, analog and mixed- signal components are now often incorporated together onto the same chip. Further, Deep- submicron and parasitic effects are increasingly playing a larger (and undesirable) role in transistor behavior. Due to these effects we cannot solely rely on digital/logic simulation, but must also employ analog simulation to obtain accurate performance of Integrated circuits. The size and complexity of the electronics systems today makes transistor level simulation times prohibitively large. Due to these issues, Analog and Mixed Signal Hardware Description Languages (AMS-HDL) have become increasingly important for modeling and simulating mixed-signal and mixed-technology systems. Significant AMS languages such as Verilog AMS and VHDL-AMS potentially provide improved simulation times and multiple levels of modeling abstraction. This thesis investigates a new continuous, dynamic charge-based MOS transistor model that incorporates various deep-submicron effects. Based on the latest EKV Model description (version 3.0), our model is implemented in VHDL-AMS. Evaluated for accuracy, performance and robustness the model demonstrates up to 10% improvement for benchmark circuits incorporating 1 to 14 transistors. Further, the model consistently executed to completion more often than for equivalent SPICE models. Thus, the new model described in this work is robust and thereby satisfies the goals of the thesis.
Advisors/Committee Members: Carter, Dr. Harold W.
More Like This
10.
BAJAJ, RASHMI.
EFFICIENT TASK SCHEDULING ALGORITHM FOR NETWORK OF HETEROGENEOUS WORKSTATIONS.
Degree: MS, Engineering : Computer Engineering, 2001, University of Cincinnati
► Optimal scheduling of parallel tasks with some precedence relationship, onto a distributed-memory…
(more)
▼ Optimal scheduling of parallel tasks with some precedence relationship, onto a distributed-memory machine is known to be a strong NP-hard problem. The complexity of the problem increases when task scheduling is to be done on a network of heterogeneous workstations (NoWs), where workstations may not be identical and may take different amount of time to execute the same task. This dissertation presents a Task duplication based scheduling Algorithm for Network of Heterogeneous workstations (TANH), with complexity O(V 2 ), which provides optimal results for applications represented by Directed Acyclic Graphs (DAGs), provided some simple conditions on task computation and network communication time could be satisfied. The performance of the algorithm is illustrated by comparing the scheduling time with an existing scheme BIL, for heterogeneous systems. We also observe that TANH provides speed-ups of 6 to 40 for some practical DAGs with upto 3000 nodes and the number of edges varying from 4000 to as high as 25000 edges, if adequate duplication is allowed. The flexibility of scaling to higher or lower number of workstations, as per their availability is also discussed. Some problems for future work are also briefly outlined.
Advisors/Committee Members: Agrawal, Dr. Dharma P.
Keywords: distributed computing; task duplicaiton algorithm; optimal algorithm; network of workstations
More Like This
11.
BALAKRISHNAN, GEETA.
ITERATIVE RELAXATION ALGORITHM: AN EFFICIENT AND IMPROVED METHOD FOR CIRCUIT SIMULATION USED IN SIERRA: VHDL-AMS SIMULATOR.
Degree: MS, Engineering : Computer Engineering, 2002, University of Cincinnati
► Simulation is a means of validating and verifying the functionality of an…
(more)
▼ Simulation is a means of validating and verifying the functionality of an electronic circuit. The success of any semiconductor industry depends greatly on the die-yield and throughput. Simulation is an excellent method to provide feedback to the designer when designing large systems, so that modifications in design and implementation can be done during the initial stages of design before the actual hardware implementation of the chip. Simulation helps the designer to identify the key factors affecting the design and try to enhance performance. VHDL-AMS is an extension of VHDL, the hardware description language supporting the digital circuit environment. The AMS extension enables modeling of analog and mixed signal circuits, thereby extending the modeling horizons. VHDL-AMS, an IEEE approved high-level design language for mixed signal multi-domain circuits support description of high-level systems with continuous dynamic behavior that can be specified as Ordinary Differential Algebraic Equations. The chief bottle-neck in mixed-signal simulation is speed. The solve time at each time step is large which in turn contributes to the total simulation time. Hence a method to improve the solve time is definitely a welcome, as it contributes to the overall performance improvement. The Relaxation algorithm studied and implemented in this thesis is a method explored to improve the performance of the simulator. It is based on the use of iterative algorithms as against the conventional direct method of solution. Spectral radius evaluation which further reduces the solve time from a complexity of O(n3) to O(n) is incorporated into the relax algorithm to further improve overall performance. This thesis proposes an improvement in speed of at least 5% for digital, analog and mixed circuits.
Advisors/Committee Members: Carter, Dr. Harold W.
Keywords: relaxation algorithm; mixed signal simulation; VHDL-AMS; spectral radius approach; relax factor
More Like This
12.
BALASUBRAMANIAN, SHYAM SUNDAR.
A NOVEL METHODOLOGY FOR MODELING PERFORMANCE PARAMETERS OF ANALOG CIRCUITS.
Degree: MS, Engineering : Computer Engineering, 2004, University of Cincinnati
► The need to explore large design spaces and the large computational overhead…
(more)
▼ The need to explore large design spaces and the large computational overhead in full circuit simulations has been the driving factor for the use of performance estimation techniques in automated synthesis of analog and mixed-signal circuits. One such technique called Macromodeling has been used extensively nowadays owing to their accuracy (comparable to the simulators) and speed. The smaller evaluation time and comparable accuracy of these models to the simulators like HSPICE have made them quite popular for use in synthesis algorithms (which optimize a cost function based on performance constraints). Traditional Macromodeling approaches involve the generation and use of a separate macromodel for each performance parameter and consequently, does not support the dynamic addition of performance parameters. The addition of a new performance constraint necessitates charactarization data regeneration and model development phase and consequently, a large time overhead. In this thesis, we present a new approach wherein we develop a model for producing the entire AC response curve rather than separate models for each performance parameter. The model consists of a set of regressors (which have been implemented using polynomials followed by regression on the polynomial coefficients using neural networks) which take in the design variables as input and produce the AC response as output very quickly. Thus, the addition of a performance parameter requires the evaluation of that parameter from the calculated response and thus, eliminates the data re-generation and model development time overhead. In essence, the proposed approach supports and requires very minimal overhead for the dynamic addition of performance parameters. The performance parameters, calculated from the evaluated response, are then used for the cost function optimization in the synthesis loop.
Advisors/Committee Members: Vemuri, Dr. Ranga.
Keywords: Analog Macromodeling; Modeling Performance Parameters
More Like This
13.
Balasubramanian, Sundar Rajan.
A Parallel Hardware Architecture for Fast Signature Generation of Rainbow.
Degree: MS, Engineering : Computer Engineering, 2007, University of Cincinnati
► This thesis deals with the conceptualization, design and implementation of an area-time…
(more)
▼ This thesis deals with the conceptualization, design and implementation of an area-time efficient architecture for the multivariate quadratic signature scheme, Rainbow. Multivariate Public Key Cryptosystem (MPKC) schemes are in general much more computationally efficient than number theoretic-based schemes. This has led to many new constructions and Rainbow is one of them. It belongs to the class of mixed schemes under Multivariate Quadratic (MQ) constructions [27]. The software implementation of Rainbow has been submitted to ECRYPT Benchmarking of Assymetric Systems (eBATS) [14]. We investigate the requirements of implementing Rainbow in hardware and demonstrate its efficiency when compared to other schemes. As a result of the investigation, one of the important contributions of this thesis is the design and implementation of hardware-optimized, highly parallelized Gaussian elimination architecture, named G-SMITH (Extended- Scalable Matrix Inversion and Triangularization Hardware) [3]. This architecture is adapted for Rainbow, nevertheless it can be used by virtually any multivariate scheme, which needs to solve linear system of equations over GF(2l) in its central mapping function. Rainbow also involves affine linear transformations as a part of the signature generation procedure, for which we have re-used the G-SMITH hardware itself, thereby saving on area. As a result, the proposed Rainbow datapath architecture requires an area of 63,593 gate equivalents and computes the signature in 804 clock cycles. The area-time requirements of Rainbow, thus demonstrate that mixed MQ schemes offer massive parallelism and have the capability of generating signatures much faster than the legacy schemes such as RSA and ECDSA.
Advisors/Committee Members: Carter, Dr. Harold W.
Keywords: Multivariate Signature Schemes; special-purpose hardware; Rainbow; G-SMITH; SMITH
More Like This
14.
BANERJEE, SUMON.
Spatial and Temporal Correlation and Extracting Critical Attribute in a Three dimensional Wireless Sensor Network.
Degree: MS, Engineering : Computer Engineering, 2008, University of Cincinnati
► We exploit spatial correlation in a 3-dimensional wireless sensor network by comparing…
(more)
▼ We exploit spatial correlation in a 3-dimensional wireless sensor network by comparing polynomial regression and kernel regression technique. A binary tree is created where each level of the tree is characterized by a kernel function. The sensing nodes report their position co-ordinate and sensed attribute to the nearest tree node which computes the coefficients of regression. The temporal correlation of sensor data is exploited by a scheme where the critical attributes of a 3D region is evaluated by analyzing the regression polynomial and the existing data aggregation technique is modified to eliminate the need of performing regression at every tree node when a data value changes. Lastly, for stationary actors, the critical co-ordinates are utilized through Voronoi tessellations drawn in 2-D with the critical co-ordinates as their centers. For mobile actors, a bipartite matching algorithm is proposed which makes an effort to accommodate the actor requirement of each event region.
Advisors/Committee Members: Agrawal, Dharma.
Subjects: Computer science
More Like This
15.
BAPAT, SACHIN VASUDEO.
THE PERFORMANCE EVALUATION OF VHDL-AMS SIMULATORS BY CREATING LARGE, SCALABLE VHDL-AMS MODELS.
Degree: MS, Engineering : Computer Engineering, 2002, University of Cincinnati
► A circuit simulator is an essential tool for every electronic design engineer.…
(more)
▼ A circuit simulator is an essential tool for every electronic design engineer. As many modern electronic systems contain a digital as well as an analog circuitry, a mixed-signal simulator is becoming an essential element for the modern design environment. A mixed-signal simulator typically consists of a digital kernel, an analog kernel and a method for synchronization. Analog kernels execute slowly compared to the digital kernels and thus are computationally expensive. Hence the developers of mixed-signal simulators should aim at reducing the simulation time by analyzing the simulator performance. This research is on the creation and an application of large, scalable models to evaluate the performance of VHDL-AMS simulators. We have created two VHDL-AMS models that scale and that possess a rich set of language features. One is termed as a RLC model and the other one as a SRAM model. The simulator performance was measured and analyzed by simulating the two models on a mixed-signal simulator. For this research, we have used a Sierra mixed-signal simulator developed at University of Cincinnati.
Advisors/Committee Members: Carter, Dr. Harold.
Keywords: VHDL-AMS; mixed signal simulation
More Like This
16.
BASU, SHUBHANKAR.
Performance Modeling and Optimization Techniques in the Presence of Random Process Variations to Improve Parametric Yield of VLSI Circuits.
Degree: PhD, Engineering : Computer Engineering, 2008, University of Cincinnati
► As semiconductor industry continues to follow Moore's Law of doubled devicecount every…
(more)
▼ As semiconductor industry continues to follow Moore's Law of doubled devicecount every 18 months, it is challenged by the rising uncertainties in the manufacturing process for nanometer technologies. Manufacturing defects lead to a random variation in physical parameters like the dopant density, critical dimensions and oxide thickness. These physical defects manifest themselves as variations in device process parameters like threshold voltage and effective channel length of transistors. The randomness in process parameters affect the performance of VLSI circuits which leads to a loss in parametric yield. Conventional design methodologies, with corner case based analysis techniques fail to predict the performance of circuits reliably in the presence of random process variations. Moreover, the analysis techniques for detection of defects in the later stages of the design cycle result in significant overhead in cost due to re-spins. In recent times, VLSI computer aided design methodologies have shifted to statistical analysis techniques for performance measurements with specific yield targets. However, the adoption of statistical techniques in commercial design flows has been limited by the complexity of their usage and the need for generating specially characterized models. This also makes them unsuitable in repeated loops during the synthesis process. In this dissertation, we present an alternate approach to model and optimize the performance of digital and analog circuits in the presence of random process variations. Our work is targeted for a bottom-up methodology providing incremental tolerance to the circuits under the impact of random process variations. The methodologies presented, can be used to generate fast evaluating accurate macromodels to compute the bounds of performance due to the underlying variations in device parameters. The primary goal of our methodology is to capture the statistical aspects of variation in the lower levels of abstraction, while aiding deterministic analysis during the top level design optimization. We also attempt to build our solutions as a wrapper around a conventional design flow, without the requirement for special characterization. The modeling and optimization techniques are perfectly scalable across technology generations and can find practical usage during variation-tolerant synthesis of VLSI circuit performance.
Advisors/Committee Members: Vemuri, Ranga.
Subjects: Computer science
Keywords: variation tolerant designs; variation aware modeling, macromodels, spline, interval-valued data, center and range, regression, PCA
More Like This
17.
BHALGAT, ASHISH ZUMBARLAL.
INSTRUCTION SCHEDULING TO HIDE LOAN/STORE LATENCY IN IRREGULAR ARCHITECTURE EMBEDDED PROCESSORS.
Degree: MS, Engineering : Computer Engineering, 2001, University of Cincinnati
► Modern computers are taking increasing advantage of the instruction-level parallelism (ILP) available…
(more)
▼ Modern computers are taking increasing advantage of the instruction-level parallelism (ILP) available in application programs. Advances in the architectural design of the Application Specific Instruction Core (ASIC) embedded processors often result in complex and irregular processor architectures. Most of the modern embedded processors use both pipelining and multiple instruction issue techniques in order to execute the instructions in parallel and run the application programs much faster. Performance of such Very Long Instruction Word (VLIW) architectures is mainly dependent on the capability of the compiler to detect and exploit the ILP. To take the advantage of the inherently available parallelism in the code, instruction are reordered so that the length of code schedule can be reduced. Thus, code motion of instructions may minimize the overall cycle count resulting in better code execution efficiency. However, code reordering is often constrained by the dependencies among the instructions due to the control and data flow inherent in the code. Further, compile time instruction scheduling for such irregular architectures is a challenging problem due to the architectural constraints imposed on the restructuring of instructions. In this thesis, we present a framework to restructure the instructions to exploit the ILP through the parallel instructions available in the Instruction Set Architecture (ISA) of our EPIC VLIW Digital Signal Processor. We focus on the memory access instructions, loads and stores, and optimize the schedule to hide the load/store instruction latency.
Advisors/Committee Members: Pande, Santosh.
Keywords: DSP; VLIW; Dynamic Scheduling; Just In Time (JTT) Scheduling; Compiler Optimization
More Like This
18.
Bharkhada, Bharat Kishore.
Efficient Fpga Implementation of a Generic Function Approximator and Its Application to Neural Net Computation.
Degree: MS, Engineering : Computer Engineering, 2003, University of Cincinnati
► Every neuron or processing element of an Artificial Neural Network (ANN) implementation…
(more)
▼ Every neuron or processing element of an Artificial Neural Network (ANN) implementation requires an activation function. In the digital implementation of an ANN, the activation function is most widely implemented as a lookup table, and the accuracy of the output of the processing element depends partially on the number of words stored in the lookup table. The disadvantage with this approach is that, to achieve better results, the lookup table goes on increasing in size and often becomes large and unwieldy. In this thesis we explore the possibility of replacing the lookup table with direct computation of the activation function. As a case study, we compute the widely used activation function, the sigmoid function, by using a generic third order polynomial evaluator which is based on prior work addressing the problem of efficient function approximation for a system on a chip. The sigmoid function is approximated with a set of polynomials with integer coefficients. This approach results in a huge reduction in the memory required by the processing element. Booth encoding and Wallace tree techniques are used to further optimize the computation. The project is implemented in VHDL. The synthesis of the implementation and architectural simulations including place and route and timing analysis are carried using the Altera FLEX 10K family of devices. Synthesis and architectural simulations are also done in Synopsys. We show that our implementation achieves a large saving in memory and equivalent accuracy when compared with the lookup table approach, at the cost of some extra logic and execution time. We also show that our implementation achieves higher accuracy than other sigmoid approximations proposed in the literature. The current implementation can also generate a programmable sigmoid function and would allow, with minor changes and no increase in memory requirements, two to four different choices of slope for the sigmoid itself.
Advisors/Committee Members: Purdy, Dr. Carla.
Keywords: FPGA Activation Function; hardware activation function; sigmoid function; neural network activation function
More Like This
19.
BHATTACHARYA, PRASUN.
COMPARISON OF SINGLE-PORT AND MULTI-PORT NoCs WITH CONTEMPORARY BUSES ON FPGAs.
Degree: MS, Engineering : Computer Engineering, 2006, University of Cincinnati
► Systems-on-chip brought several cores onto a single chip. But, as more cores…
(more)
▼ Systems-on-chip brought several cores onto a single chip. But, as more cores are being put onto a single chip, the on-chip communication resource, which is usually a bus started getting overburdened. With its inherent problems like scaling, inability to support parallelism etc. the on-chip communication soon became a performance bottleneck. Networks-on-chip has been proposed as a solution for on-chip communication. Thus we aim to compare the relative performance of contemporary against indigenously built cores of NoCs. We first built a router keeping in mind the area limitations of FPGAs. Then we extract the timing information by simulations of the Bus and Router cores on FPGAs. Finally, for comparison of buses and NoCs we develop a cycle accurate simulator using the timing values obtained by simulation of the cores. It was developed in C++ for both the bus and the NoC to compare the two on a set of benchmarks.
Advisors/Committee Members: Vemuri, Dr. Ranga.
Keywords: NoC, Routers, SoC, FPGA
More Like This
20.
BHOOPATHY, MANIVANNAN.
EXPLOITING A MULTI-LEVEL MODELING TECHNIQUE WITH APPLICATION TO THE ANALYSIS OF A SUCCESSIVE APPROXIMATION ANALOG-TO-DIGITAL CONVERTER.
Degree: MS, Engineering : Computer Engineering, 2005, University of Cincinnati
► In recent years mixed-signal system-on-chip have gained wide usage. The time to…
(more)
▼ In recent years mixed-signal system-on-chip have gained wide usage. The time to market of these devices are affected by the constrains in prototyping. VHDL-AMS provides the capability of behavioral modeling of mixed-signal designs, which is not available in the conventional SPICE modeling. Using VHDL-AMS, a top-down design approach can be utilized for the mixed-signal systems. This method has been claimed to reduce the time-to-market, when compared to the conventional bottom-up approach used for analog and mixed-signal designs. The main reason for this is the reduced simulation time of top level models (i.e. behavioral models). In this thesis work, we study a modeling approach for a generic successive approximation analog-to-digital converter and its components using VHDL-AMS at varying levels of abstraction. Methods for introducing system features and non-idealities at various abstractions are also discussed.
Advisors/Committee Members: Carter, Dr. Harold W.
Keywords: VHDL-AMS; mixed-signal modeling
More Like This
21.
BRAND, JESSE EDWARD.
AN ANALYSIS AND COMPARISON OF DISTRIBUTED OPTIMISTIC TIME SIMULATION USING THE SPEEDES AND WARP IV SIMULATORS.
Degree: MS, Engineering : Computer Engineering, 2005, University of Cincinnati
► At the United States Air Force Research Laboratory (AFRL) distributed discrete event…
(more)
▼ At the United States Air Force Research Laboratory (AFRL) distributed discrete event simulation (DDES) is vital to the creation and testing of new technology in areas from flight characteristics of unmanned air vehicles (UAV) to the communications a missile uses to adapt to a moving target. The evaluation of AFRL’s distributed simulator SPEEDES (Synchronous Parallel Environment for Emulation and Discrete Event Simulation) against WarpIV, another commercial distributed simulator, analyzes the performance of these simulators under varying conditions. The conditions are created by an adjustable model that was created to mimic the intense mathematical calculations required for the simulation of an aircraft’s aerodynamics. The raw data retrieved from the adjustable model consisted of total execution times. Statistical analysis is performed on the data to compare the total execution times of SPEEDES to the total execution times of WarpIV.
Advisors/Committee Members: Carter, Dr. Harold.
Keywords: Distributed Discrete Event Simulation
More Like This
22.
CHACKO, BABU.
A VHDL-AMS BSIM4.1 MODEL.
Degree: MS, Engineering : Computer Engineering, 2008, University of Cincinnati
► Today there is a continuing need for accurate and high-speed device models…
(more)
▼ Today there is a continuing need for accurate and high-speed device models for pre-simulation of large circuits before fabrication. Further, with shrinking of transistor sizes, both analog and digital circuits are sharing the same chip space in today´s integrated circuit design. As a result, mixed-signal simulators are becoming popular today.VHDL-AMS is a mixed-signal hardware design language which has the capability of modeling both digital and analog circuits at different level of abstraction. Unfortunately there are few transistor models directly implemented in VHDL-AMS. The models that do exist have largely been the result of research at Universities rather than industry-supported models. Further the transistor models that exist are oriented towards the microelectronic technology domain above 100nm. So far there exist no BSIM transistor models in VHDL-AMS capable of accurately modeling transistors in the sub-100 nm range. A candidate for a good deep submicron transistor model is the BSIM4 model. In this thesis we have used BSIM4.1 model to create a deep submicron transistor model for VHDL-AMS. It has been evaluated using realistic analog and digital test circuits for accuracy, robustness and performance. Equivalent test circuits were created in HSPICE to compare the results obtained from the VHDL-AMS model. The test results show that the BSIM4.1 VHDLAMS model performed well for all test circuits with maximum error less than 7% and an average error less than 2%.
Advisors/Committee Members: Carter, Harold.
Subjects: Electrical engineering
More Like This
23.
Chadha, Vishal.
Design and Implementation of a Second Generation Logic Cluster for Multi-Technology Field Programmable Gate Arrays.
Degree: MS, Engineering : Computer Engineering, 2005, University of Cincinnati
► One limitation of current FPGAs is that the user is limited to…
(more)
▼ One limitation of current FPGAs is that the user is limited to strictly digital electronic designs and are not suitable for multi-technology applications. In 2002, the novel idea of a Multi-technology Field Programmable Gate Array was proposed to extend the flexibility and reusability benefits of conventional FPGAs into multi-technology domain. But the chip design done for that work was not well suited for implementations in modern systems and was not compatible with modern CAD resources. Further, digital logic clusters did not include a dedicated carry-chain for arithmetic operations as in many FPGAs. In this thesis, research has been done to make the Multi-Technology Logic Cluster design much faster, smaller and versatile by using improved process technology, floorplanning and data processing capabilities so that these components match the performance expected from current applications. Hence, this is the next step in evolution of MT-FPGAs to provide high-performance solutions for complex applications.
Advisors/Committee Members: Beyette Jr., Dr. Fred R.
Keywords: ASIC; Application specific integrated circuit; CMOS; Complementary Metal Oxide Semiconductor. Technology used to manufacture silicon; integrated circuits; Delay flip-flop or D-flop; The input is copied to the output delayed by one clock cycle; FPGA
More Like This
24.
CHAKRABORTY, RITOCHIT.
SYMBOLIC TIME DOMAIN BEHAVIOR AND PERFORMANCE ANALYSIS OF LINEAR ANALOG CIRCUITS.
Degree: MS, Engineering : Computer Engineering, 2006, University of Cincinnati
► Automated design of analog circuits involves circuit sizing, a process of assigning…
(more)
▼ Automated design of analog circuits involves circuit sizing, a process of assigning numerical values to unknown parameters of a fixed circuit topology. With the advent of exemplary concepts based on determinant decision diagrams (DDDs), symbolic analysis techniques have begun to play a pivotal role in analog synthesis. Their strength lies in the ability to incorporate circuit parasitics. In this thesis, a new symbolic pole extraction algorithm based on graph theory has been proposed. Techniques aimed at developing time domain symbolic behavioral and performance models in order to expedite circuit synthesis are described. The CAD tool STDA incorporates symbolic models that analyze the time domain behavior of different classes of analog circuits. The symbolic approach to optimization-based circuit synthesis has been suggested as an alternative to the traditional numerical approach. STDA is tested extensively on a set of benchmark circuits to assess its capability, accuracy and efficiency as a CAD tool.
Advisors/Committee Members: VEMURI, Dr. RANGA.
Keywords: Analog Circuit Synthesis; Symbolic Analysis; Symbolic Newton-Iteration; Pole Extraction
More Like This
25.
CHAKRAVARTY, SWAPNAJIT.
SELF-ORGANIZATION AND AGING IN NETWORK GLASSES.
Degree: MS, Engineering : Computer Engineering, 2003, University of Cincinnati
► Ternary P x Ge x Se 1-2x glasses in the 0 <…
(more)
▼ Ternary P x Ge x Se 1-2x glasses in the 0 < x < 0.26 composition range, in their fresh and aged state are examined in temperature modulated DSC, Raman scattering and molar volume measurements. Bimodal endotherms are observed, with the high-T endotherm representing a glass transition temperature, while the sub-T g endotherm an activated process. We speculate that the latter is associated with P 4 units [(Se=P(Se 1/2 ) 3 )] frozen at high T converting to P 3 [(P(Se 1/2 ) 3 )] ones as the glass is heated. The sub-T g endotherm up-shifts in temperature with aging and in some cases merges with T g endotherm. T g (x) accessed from the reversing heat flow are found to increase with x as a power-law, displaying a weak cusp near x = 0.04. The non-reversing enthalpy is found to display a global minimum in the 0.09 < x < 0.145 range identified with the thermally reversing window . Raman scattering reveals that isostatically rigid units of P 3 , P 4 , CS and ES Ge(Se 1/2 ) 4 comprise building blocks of the thermally reversing window. Raman optical elasticity measurements suggest the existence of three distinct elastic phases; floppy (x < 0.09), intermediate (0.09 < x < 0.145), and stressed rigid (x > 0.145) with two distinct elastic thresholds at x = 0.084 and x = 0.1447. The elasticity power-laws in the intermediate and stressed-rigid phases are found to be p = 1.0(1) and p = 1.49(2) respectively. The coincidence of the thermal and elastic thresholds shows that the thermally reversing window represents the self-organized phase in the present ternary. Glass compositions inside (outside) the window are characterized by absence (presence) of aging of the non-reversing enthalpy as well as molar volumes . These results reinforce the privileged nature of glasses in the window that are in a state of low free energy.
Advisors/Committee Members: Boolchand, Dr. Punit.
Keywords: chalcogenide glasses; self organization; aging; intermediate phase; phosphorus germanium selenium glasses
More Like This
26.
CHAMARTY, VINOD.
INVESTIGATION OF AN INFORMATION STRUCTURE TO SUPPORT THE ELABORATION OF SIMULTANEOUS STATEMENTS IN COMPILE-DRIVEN MIXED-SIGNAL SIMULATION.
Degree: MS, Engineering : Computer Engineering, 2004, University of Cincinnati
► The issue of performance of compile-driven mixed-signal simulation is a challenging problem…
(more)
▼ The issue of performance of compile-driven mixed-signal simulation is a challenging problem with optimization techniques researched to speed-up the various phases of simulation. The matrix load phase of the analog simulation kernel has been found to consume the largest percentage of the total simulation time. It is also known that in the worst case, the matrix load time is a cubic function of the number of equations in the system. Therefore, efforts have been directed towards reducing the matrix load time in a mixed-signal simulation paradigm. The elaborated set of Characteristic Expressions (CEs) forms the input to the matrix load phase of the analog kernel. The CEs are formed either as a result of elaborating simultaneous statements or because of the association of the quantities and terminals. A reduction in the elaborated set of CEs would result in the reduction of both the matrix load and matrix solve times. The current data structures do not support the reduction of the elaborated set of CEs. This thesis presents the design of a new Information Structure (IS) to support the modification and reduction of CEs and sets of CEs respectively. We exploit this design to improve the performance of compile-driven mixed-signal simulation. A proof of concept has been provided to demonstrate the viability of the designed Information Structure.
Advisors/Committee Members: Carter, Dr. Hal.
Keywords: mixed signal simulation, elaboration, characteristic expressions, reduction of elaborated set, SIERRA2
More Like This
27.
CHANDA, PRITAM.
A BANDWIDTH ALLOCATION FRAMEWORK USING TIME ADAPTABILITY FOR MULTIMEDIA TRAFFIC IN WIRELESS AND MOBILE CELLULAR NETWORKS.
Degree: MS, Engineering : Computer Engineering, 2005, University of Cincinnati
► Next generation wireless and mobile cellular networks are expected to support multimedia…
(more)
▼ Next generation wireless and mobile cellular networks are expected to support multimedia applications. High user mobility and inherent instability of wireless channels make quality of service (QoS) provisioning a challenging issue in wireless and mobile networks. In this thesis, we propose a novel concept of time adaptability and introduce two adaptive time bandwidth allocation schemes, namely, adaptive time period (ATP) and flexible adaptive time period (FATP) for QoS provisioning in wireless and mobile cellular networks for variable bandwidth multimedia calls. With time adaptability, each call not only specifies the minimum and maximum bandwidth requirements in terms of basic bandwidth units (bbu), but also specifies a step size and an adaptive period. Step size is the bbu constituting each layer of adaptive multimedia. Adaptive period is the time period specified by a call over which the bandwidth change incurred by the call cannot exceed the step size for that call. This, accompanied by temporary bandwidth borrowing from the ongoing calls not only reduces forced termination probability of handoff calls and ensures that each call gets a fare share of the available system bandwidth but also helps to decrease large bandwidth fluctuations at the end mobile users running multimedia applications such as video conferencing or online gaming. Extensive simulation results show that our proposed schemes maintain a low forced termination probability for handoff calls and significantly reduce bandwidth variations.
Advisors/Committee Members: Zeng, Dr. Qing-An.
Subjects: Computer Science
Keywords: Bandwidth allocation; QoS; Adaptive multimedia; time adaptability; Call admission control
More Like This
28.
CHEN, TAO.
Multi-FPGA Partitioning Using Simulated Annealing.
Degree: MS, Engineering : Computer Engineering, 2004, University of Cincinnati
► Partitioning becomes necessary when placing a circuit with a large number of…
(more)
▼ Partitioning becomes necessary when placing a circuit with a large number of gates on chips with area limitation, I/O limitation, or cost consideration. Given the circuit hypergraph, the target architecture and constraints, the partitioning engine divides the design into subsets in a reasonable time so that the cost is optimized. Simulated annealing is a move-based non-deterministic partitioning algorithm. It allows both uphill and downhill moves in order to achieve a global optimum. The core of simulated annealing algorithm is the Metropolis procedure. The simulated annealing partitioning results are controlled by its parameters. In the thesis, the parameters are classified into three categories: temperature-related parameters that control the searching broadness, M-related parameters that control the searching range for each temperature, and threshold parameters that control the acceptance rates. The most difficult part in simulated annealing implementation is to determine the proper parameters for a given hypergraph to make an optimal tradeoff between the result quality and execution time. Circuit topology is introduced to describe the characteristics of the hypergraph. By analyzing some basic parameters, the thesis concludes some common characteristics that lead to determine an optimal implementation schema. PAUSE, a real-world partitioning project, is used in the thesis to reveal how to use simulated annealing for multi-FPGA partitioning in a partitioning environment. Multiple techniques are used to achieve an effective and seamless implementation in PAUSE.
Advisors/Committee Members: Vemuri, Dr. Ranga.
More Like This
29.
Chen, Yuan.
A Fast, Passive and Accurate Model Generation Algorithm for RLCG Transmission Lines with Skin Effects.
Degree: MS, Engineering : Computer Engineering, 2005, University of Cincinnati
► Accurate simulation of lossy transmission lines with skin effects has always been…
(more)
▼ Accurate simulation of lossy transmission lines with skin effects has always been difficult or at least inefficient. Although modeling lossy transmission lines without skin effects can be carried out efficiently and accurately, including accurate skin effect model either affect accuracy or efficiency. Skin effect is accurately approximated using the simple form A+B√s at high frequencies, i.e. when s is large. However, this form is not passive. Passivity guarantees stability. Since a transmission line is a passive device, its model should also be passive such that the simulation depending on it is stable. If skin effect is approximated by A+B√s and directly incorporated into a model, the simulation based on that model may become unstable. In this thesis, a method to generate a passive, accurate and compact model for a lossy transmission line with skin effect is introduced. The method is developed on a RLC lumped equivalent circuit of a transmission line. By applying a passive model order reduction algorithm and exploring the properties of the transmission line equivalent circuit, we found out a novel way to map the model reduction process into solving integrals. By matching moments implicitly, a passive and accurate model for a lossy transmission line with skin effect can be generated rapidly.
Advisors/Committee Members: Carter, Dr. Harold.
Keywords: Model Order reduction; Split Congruence Transformations; Lossy Transmission Line; Skin Effect
More Like This
30.
CHIRUMAMILLA, JAYABHARATH.
A MODIFIED PRECONDITIONING FRAMEWORK FOR THE GAUSS-JACOBI METHOD APPLIED TO CIRCUIT SIMULATION.
Degree: MS, Engineering : Computer Engineering, 2006, University of Cincinnati
► Simulation is a means of evaluating a hardware circuit and to verify…
(more)
▼ Simulation is a means of evaluating a hardware circuit and to verify design alternatives. It is an important phase of the design cycle. Mixed-signal simulation allows simulating a system with both digital and analog components. Such systems are becoming more and more commonplace. Digital components exhibit discrete behavior while analog components exhibit continuous behavior. It is in the best interests of the design community to have a fast mixed-signal simulator. The continuous time simulator, which is one part of the mixed-signal simulator deals with simulating the analog components. The input to a continuous time simulator is a system of Ordinary Differential Algebraic Equations (ODAEs). One of the steps in the simulation of a system of ODAEs is the linear system solution. Typically a direct numerical method like LU decomposition is used for a linear system solution. It has been shown that the Gauss-Jacobi method can offer a performance speed-up compared to the LU decomposition method. In this thesis we attempt to further speed-up the execution of Gauss-Jacobi solver by preconditioning the coefficient matrix. We then present several interesting results to see how exactly the preconditioning approach relates to the execution time of the Gauss-Jacobi method.
Advisors/Committee Members: Carter, Dr. Harold W.
Keywords: preconditioning gauss jacobi circuit simulation
More Like This
[1] [2] [3] [4] [5] [6] [7]
