Department: EECS - Computer Engineering ![[clear]](close-x.png "Remove this limiter")
31 matches in the database.
These are records: 1 - 30.
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1.
Al-Omari, Huthaifa Abdelhameed.
Analysis and Modeling of One-Way Network Delay Variations.
Degree: PhD, EECS - Computer Engineering, 2009, Case Western Reserve University
► One-way delay variations adversely affect the performance of several real-time applications that…
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▼ One-way delay variations adversely affect the performance of several real-time applications that require accurate prediction of packet delivery times. This thesis study the random behavior of one-way delay variations based on extensive real-time experiments that we have carried over the Internet using fifty strategically located wired and wireless hosts. Specifically, in this thesis we examine whether forward and reverse one-way delay variations can be adequately represented by specific distribution functions. Then, we explore the degree of dependency in both forward and reverse one-way delay variations by investigating their autocorrelation and cross-correlation. Furthermore, we propose a scheme that uses several one-way delay variation models to smooth out delay jitter in Cyber-Physical Systems (CPSs) with no clock synchronization.
Advisors/Committee Members: Papachristou, Christos.
Subjects: Computer science
Keywords: Play-Back Delay; RTT; DELAY VARIATIONS; rcp; DELAY
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2.
Al-Qudah, Zakaria.
EFFICIENCY AND SECURITY ISSUES IN GLOBAL HOSTING PLATFORMS.
Degree: PhD, EECS - Computer Engineering, 2010, Case Western Reserve University
► Shared application-level Web infrastructures such as Content Distribution Networks(CDNs) and computing utility…
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▼ Shared application-level Web infrastructures such as Content Distribution Networks(CDNs) and computing utility platforms (e.g., Amazon EC2) have become an essential part of the Internet. As these platforms mature, it is becoming plausible for them to converge to a comprehensive form of service whereby the service provider is responsible for supplying businesses with all their infrastructure needs in a scalable, efficient, and transparent manner. This dissertation addresses three problems toward realizing this type of comprehensive platforms. The first problem is the high cost and long delay of enacting Web application (re-)placement decisions which constrains application placement algorithms in terms of the rate at which placement decisions could be revisited. In this regard, we propose, implement, and evaluate various mechanisms to significantly reduce the amount of time and resources needed to enact application placements. In the second problem we address the issue of connection disruptions in hosting platforms that use IP anycast mechanisms to route end-users’ requests to hosting servers. Connections can be disrupted in these platforms because IP routes can change in the middle of a download which can cause packets from a connection to arrive at a different server, which would reset the connection and thus disrupt the download. To this end, we propose a simple and efficient mechanism to handle connection disruptions in these platforms. Lastly, we study the issue of Web timeouts in a Web hosting platform. We find that there is a big mismatch between the timeouts exhibited in today’s Web servers and the actual time Web clients take to perform various activities. This opens the door for the so-called claim-and-hold DoS attacks, where an attacker claims server resources and holds them as long as possible while spending minimal amount of resources of its own. We propose to significantly reduce timeouts when the server becomes low on resources, and we demonstrate how this can protect servers against these attacks.
Advisors/Committee Members: Rabinovich, Michael.
Subjects: Computer science; Engineering
Keywords: EFFICIENCY; SECURITY; GLOBAL HOSTING PLATFORMS; HOSTING PLATFORMS; CDN; TIMEOUT; ANYCAST
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3.
Alzoubi, Khawla Ali.
NANO-ELECTRO-MECHANICAL SWITCH (NEMS) FOR ULTRA-LOW POWER PORTABLE EMBEDDED SYSTEM APPLICATIONS: ANALYSIS, DESIGN, MODELING, AND CIRCUIT SIMULATION.
Degree: PhD, EECS - Computer Engineering, 2010, Case Western Reserve University
► To overcome the excessive quiescent dissipation in Nanometer-CMOS technology, especially in portable…
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▼ To overcome the excessive quiescent dissipation in Nanometer-CMOS technology, especially in portable embedded system computing where the energy efficiency, cooling system and environment changes are more important than the speed. In this work, I investigated a Nano-Electro-Mechanical Switch (NEMS) that offers novel characteristics in terms of virtually zero leakage current, low operating voltage ~1-1.2 V, high switching speed ~1-1.4 ns, and footprint size. Furthermore, this switch can be fabricated easily by using the modified CMOS fabrication process and equipment. These features make this switch a good candidate to address the energy efficiency problem in Nanometer-CMOS technology without extreme cost. In this work, the NEMS switch that mentioned previously is studied. The study involves analysis, design, modeling, and building a circuit simulator. This switch is designed to mimic CMOS transistor’s structure and configure to N-channel and P-channel similar to NMOS and PMOS correspondingly in CMOS technology. Thus, the design of NEMS computational and sequential circuits can be expedited by using CMOS design concepts and CAD tools. This switch is designed to have simple structure that can be fabricated easily by using the modified CMOS fabrication process and equipment. In modeling this device, a new approach is developed to derive an accurate device circuit simulation model (Macromodel). In this approach, a Finite Element Analysis (FEA) physical device model is constructed. Using this FEA physical model and the fabricated device measurements, an accurate device circuit simulation model (Macromodel) is derived and calibrated. The derived Macromodel is capable of mimicking the physical device in a circuit environment in a circuit environment within average error is around 10% to the physical device model. To evaluate an arbitrary NEMS circuit accurately, a circuit simulator is built. The circuit simulator uses the derived circuit simulation model and the circuit simulation techniques. Finally, to demonstrate the power advantage of using CNEMS technology in implementing computational and sequential circuits, circuit simulation experiments were conducted. The experimental results reveal significant improvements in reducing the quiescent power dissipation in CNEMS benchmark circuits over the counterpart Nanometer-CMOS benchmark circuit, moreover, improvements in reducing the active power dissipation in CNEMS circuits over Nanometer-CMOS is demonstrated.
Advisors/Committee Members: Saab, Daniel.
Subjects: Computer science; Electrical engineering; Engineering; Mechanical engineering
Keywords: NEMS; NEMS SWITCH; PHYSICAL DEVICE; CIRCUIT; PHYSICAL DEVICE MODEL; CMOS; 3D FEA
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4.
Bhamidipati, Harini.
SINGLE TROJAN INJECTION MODEL GENERATION AND DETECTION.
Degree: MS, EECS - Computer Engineering, 2009, Case Western Reserve University
► This thesis proposes a technique for non-destructive and functional testing of ICs…
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▼ This thesis proposes a technique for non-destructive and functional testing of ICs to detect modifications made to the design. The outsourcing of the fabrication process by semiconductor manufacturers has made IC design vulnerable to third party modifications and placed a risk on the reliability and security of hardware systems. These hardware modifications/Trojans are carefully injected so that they cannot be detected using regular functional testing techniques. Once injected, a Trojan can perform any functionality from resetting the circuit to transmitting signals to propagating incorrect signals to the circuit output. In this work we present a technique for injection, modeling and detection of Trojans. Here the inputs of a Trojan are identified using proximity estimation techniques and the Trojan is modeled as a black box with the identified set of IOs. Then the test patterns for the detection of Trojans are generated using a modified form of ATPG. In our experiments we generated the test patterns for combinational and sequential Trojans in various benchmark circuits. Then we injected Trojans in some of the circuits and performed fault simulation to test the efficiency of the generated patterns.
Advisors/Committee Members: Saab, Daniel.
Subjects: Electrical engineering
Keywords: Trojan Inputs; Circuit; detection of Trojans; Test pattern; Nodes; side channel
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5.
Brown, Nathan D.
Accelerating SEM Depth Map Building with the GPU.
Degree: MS, EECS - Computer Engineering, 2010, Case Western Reserve University
► The Scanning Electron Microscope (SEM) produces images that are a measure of…
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▼ The Scanning Electron Microscope (SEM) produces images that are a measure of the intensity of reflected electrons as the electron beam scans across the specimen. These images illustrate the structure of the specimen’s surface. The first 3D micro-graphs were produced by tilting the image plane of the SEM, then with the deflection coils. However, this was only a pair of stereo images of which one could qualitatively view the 3D structure. The depth could only be manually calculated at specifically chosen positions.A quantitative measure of the depth at each image pixel from a pair of SEM images is much more desirable. Unfortunately, even with optimizations, this calculation is rather computationally intensive on large SEM images. Running time is slow on a single CPU, and while it is easily adaptable to run in parallel, a large cluster is not available to every SEM. Luckily, this problem is also very adaptable to run on accelerators such as a low-cost GPU. In this work, the presented GPU accelerated algorithm is shown to significantly speed the generation of a depth map for a stereo SEM image pair.
Advisors/Committee Members: Cavusoglu, M. Cenk.
Subjects: Computer science; Engineering
Keywords: GPU; Stereo; Template; NCC; Template Size; DEPTH MAP
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6.
Cai, Fang.
Efficient VLSI Architectures for Non-binary Low Density Parity Check Decoding.
Degree: MS, EECS - Computer Engineering, 2011, Case Western Reserve University
► Non-binary low-density parity-check (NB-LDPC) codes can achieve better error-correcting performance than binary…
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▼ Non-binary low-density parity-check (NB-LDPC) codes can achieve better error-correcting performance than binary LDPC codes when the code length is moderate at the cost of higher decoding complexity. The high complexity is mainly caused by the complicated computations in the check node processing and the large memory requirement. In this thesis, two VLSI designs for NB-LDPC decoders based on two novel check node processing schemes are proposed. The first design is based on forward-backward check node processing. A novel scheme and corresponding architecture are developed to implement the elementary step of the check node processing. In our design, layered decoding is applied and only nm less than q messages are kept on each edge of the associated Tanner graph. The computation units and the scheduling of the computations are optimized in the context of layered decoding to reduce the area requirement and increase the speed. This thesis also introduces an overlapped method for the check node processing among different layers to further speed up the decoding. From complexity and latency analysis, our design is much more efficient than any previous design. Our proposed decoder for a (744, 653) code over GF(32) has also been synthesized on a Xilinx Virtex-2 Pro FPGA device. It can achieve a throughput of 9.30 Mbps when 15 decoding iterations are carried out. The second design is based on a proposed trellis based check node processing scheme. The proposed scheme first sorts out a limited number of the most reliable variable-to-check (v-to-c) messages, then the check-to-variable (c-to-v) messages to all connected variable nodes are derived independently from the sorted messages without noticeable performance loss. Compared to the previous iterative forward-backward check node processing, the proposed scheme not only significantly reduced the computation complexity, but eliminated the memory required for storing the intermediate messages generated from the forward and backward processes. Inspired by this novel c-to-v message computation method, we propose to store the most reliable v-to-c messages as ‘compressed’ c-to-v messages. The c-to-v messages will be recovered from the compressed format when needed. Accordingly, the memory requirement of the overall decoder can be substantially reduced. Compared to the previous Min-max decoder architecture, the proposed design for a (837, 726) code over GF(32) can achieve the same throughput with only 46% of the area.
Advisors/Committee Members: Zhang, Xinmiao.
Subjects: Computer Engineering; Electrical Engineering
Keywords: LLRs; decoder; ï¬eld; Check Node; CNU; message
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7.
Chakraborty, Rajat Subhra.
Hardware Security through Design Obfuscation.
Degree: PhD, EECS - Computer Engineering, 2010, Case Western Reserve University
► Security of integrated circuits (ICs) has emerged as a major concern at…
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▼ Security of integrated circuits (ICs) has emerged as a major concern at different stages of IC life-cycle, spanning design, test, fabrication and deployment. Modern ICs are becoming increasingly vulnerable to various forms of security threats, such as: 1) illegal use of hardware intellectual property (IP) or “IP Piracy”; 2) illegal manufacturing of IC or “IC Piracy”; 3) insertion of malicious circuits, referred as “Hardware Trojan”, in a design to cause in-field circuit malfunction, and 4) leakage of secret information from an IC. These security threats are accentuated by current IC design practices, such as the widespread use of hardware IP modules to design complex system-on-chips (SoCs). In addition, the economics of electronic manufacturing dictates widespread outsourcing of integrated circuit fabrication to off-shore facilities, which increases the vulnerability to these attacks. In this research, we explore novel hardware design approaches that incorporate a key-based design obfuscation scheme to effectively protect a design against various security threats, while incurring low hardware and computational overheads. Obfuscation is a technique that makes comprehending and reverse-engineering a design difficult. To the best of our knowledge, this is the first effort to develop a systematic and provably robust hardware obfuscation approach that enables hardware protection at different stages of the IC life-cycle. Effectiveness of these approaches for protection against IP reverse-engineering and piracy, hardware Trojan and scan-based information leakage is evaluated with benchmark circuits and open-source IP cores. The obfuscation approaches are developed for both firm (gate-level) and soft (register transfer level) IPs. The principles of the obfuscation approach have been extended to protection of embedded software against piracy and malicious modification. An enhanced secure IC design flow with associated computer-aided design (CAD) tools is also developed.
Advisors/Committee Members: Bhunia, Swarup.
Subjects: Electrical engineering
Keywords: Hardware security; design obfuscation; hardware Trojan; statistical logic testing; secure scan design; software obfuscation; secure system-on-chip design
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8.
Du, Dongdong.
Hardware Trojan Detection Using Multiple-Parameter Side-Channel Analysis.
Degree: MS, EECS - Computer Engineering, 2010, Case Western Reserve University
► Malicious alterations of integrated circuits during fabrication in untrusted foundries pose major…
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▼ Malicious alterations of integrated circuits during fabrication in untrusted foundries pose major concern in terms of their reliable and trusted .eld operation. It is ex-tremely di.cult to discover such hardware “Trojan” instances using conventional structural or functional testing strategies. In this thesis, we propose a novel non-invasive, multiple-parameter side-channel analysis based Trojan detection approach that is capable of detecting malicious hardware modi.cations in the presence of large process variation induced noise. We exploit the intrinsic relationship between dynamic current (IDDT ) and maximum operating frequency (Fmax) of a circuit to distinguish the e.ect of a Trojan from process variation induced .uctuations in IDDT . We pro-pose a vector generation approach that can improve Trojan detection sensitivity. We show that along with IDDT and Fmax, one can also use quiescent current (IDDQ) as a third parameter to increase the con.dence level during the decision making process. Simulation results with two large circuits, a 32-bit integer execution unit (IEU) and a 128-bit Advanced Encryption System (AES) cipher, show a detection resolution of 0.04% can be achieved amidst ±20% parameter (Vth) variations. The approach is also validated with experimental results using 120nm FPGA (Xilinx Virtex-II) chips. The measurement results for the IEU core show that sequential Trojans of varying size can be reliably detected by eliminating process noise.
Advisors/Committee Members: Bhunia, Swarup.
Subjects: Electrical engineering; Engineering
Keywords: Hardware Trojan, Side-Channel Analysis, Multiple-Parameter.
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9.
Harper, Jason W.
Fast Template Matching For Vision-Based Localization.
Degree: MS, EECS - Computer Engineering, 2009, Case Western Reserve University
► This thesis presents a novel vision-based localization method that uses fast template-matching…
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▼ This thesis presents a novel vision-based localization method that uses fast template-matching techniques with respect to regularly-spaced floor tiles to provide pose information. To accomplish the template matching, an edge map is created, transformed into Hough space and interpreted modulo the periodicity of the template. In this space, offsets relative to the periodicity of the floor tiles can be found. By separately tracking accumulation of periods, a global pose estimate can be determined that is immune to accumulation of incremental errors. The method is shown to be robust with respect to noise and distracter lines, and it also recognizes when a scene analysis is untrustworthy. The method is suitable for integration within a Kalman filter to contribute to improved localization.
Advisors/Committee Members: Newman, Wyatt.
Subjects: Artificial intelligence; Robots
Keywords: machine vision; template matching; robot; localization
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10.
Huang, Fangping.
Water and Fat Image Reconstruction in Magnetic Resonance Imaging.
Degree: PhD, EECS - Computer Engineering, 2011, Case Western Reserve University
► The reconstruction of water and fat images based on chemical shift-encoded MRI…
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▼ The reconstruction of water and fat images based on chemical shift-encoded MRI has been under intensive investigation ever since 1980's, due to its significance in biomedical and clinical researches. Various approaches have been proposed, but robust reconstruction with respect to high and ultra-high MRI remains challenging. Major challenges include: (1) Ill-posedness arising from the non-linear MR signal model. Multiple solutions may exist at pixels, whereas improper selection of solutions leads to severe estimation errors. (2) Large field inhomogeneity variation in MR field complicates reconstruction. Approaches validated on low field inhomogeneities may disfunction in the presence of large field inhomogeneity variation. (3) Critical demanding of biomedical and clinical applications on accuracy and robustness. Estimates must be at minimal error rate to be acceptable. Since estimation of MR field map is crucial to water and fat image reconstruction, this dissertation mainly focuses on robust recovery of field map. The approach developed with this thesis research consists of a Markov random field (MRF) based energy model for casting the estimation of field map to extensively studied MRF energy optimization, and a novel Iterated Conditional Modes (ICM) algorithm providing high-performance MRF energy optimization. Compared to MRF energy model seen elsewhere, the proposed NLR-MRF model is characteristic of non-linear least residual data cost terms and background masking accounted for improvement of accuracy and efficiency. The major components of the novel ICM algorithm are the stability tracking (ST) and median initialization algorithms. The stability tracking algorithm dynamically keeps track of iterative stability at each pixel to avoid redundant computations. It is demonstrated that with an optimal configuration, the ST algorithm can substantially speed up the ICM iterative computations with accuracy compromise. Median based algorithms are developed to address the high sensitivity of ICM to initialization. By assuming the quasi-unimodality of MR field inhomogeneity, the median-based initialization algorithm identifies all unambiguous pixels in the whole MR field, estimates the median and uniformly or block-wisely sets the median as the initial guess. Experimental validation on synthetic and a large group of in vivo 7 Tesla mouse datasets demonstrate the robustness of the proposed approach.
Advisors/Committee Members: Zhang, Guo-Qiang.
Subjects: Computer Science
Keywords: MRI; water-fat image reconstruction; stability tracking; ICM; median initialization; high-field
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11.
Jakuben, Benedict J.
Improving Graphical User Interface (GUI) Design Using the Complete Interaction Sequence (CIS) Testing Method.
Degree: MS, EECS - Computer Engineering, 2010, Case Western Reserve University
► This thesis involves designing and implementing a complex GUI system using a…
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▼ This thesis involves designing and implementing a complex GUI system using a drag-and-drop GUI tool, followed by modeling the system as a set of finite state models (FSMs) to be used as the basis for developing a suite of design and implementation tests using the concept of complete interaction sequences (CIS). The next step is identify new transitions within the FSMs corresponding to implementation tests that were not also design tests, together with defects and surprises only detected by this subset of implementation tests. These additional transitions and their associated faults (sum of defects and surprises) are then analyzed to determine the root cause of how and when they were introduced into the system and whether or not they are due to the GUI tool used to produce the GUI code. Suggestions are given on how to prevent this unintended behavior introduced by the GUI tool, not the GUI design.
Advisors/Committee Members: Zhang, Guo-Qiang.
Subjects: Computer Science
Keywords: GUI; GUI testing; GUI design; drag and drop; CIS; complete interaction sequences; GUI tool; software testing
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12.
Johnston, David A.
Parallel Multicast Overlay Networks with Probabilistic Path Selection.
Degree: PhD, EECS - Computer Engineering, 2012, Case Western Reserve University
► Smart phones, movies on demand, regulated industrial process information; the thirst for…
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▼ Smart phones, movies on demand, regulated industrial process information; the thirst for data access has never been greater and will only continue to grow. Our network infrastructure must continue to evolve to meet the ever increasing demand for data. This is especially true when many devices demand the same data at the same time. Since improvement in pure network bandwidth capabilities is only part of the solution; many researchers have investigated efficient transfer of information and a variety of solutions have been proposed. One popular solution is the multicast overlay network which can be described as a tree. Many single multicast tree solutions and multiple multicast tree solutions have been developed; however, we still need to make these solutions more efficient. This research will focus on the use of multiple multicast trees. This is often referred to as striping where one multicast tree is one stripe. Typically in these models, each multicast tree is used equally; however, not every multicast tree has the same performance. This new method, called Probabilistic Multicast Trees (PMT), will build upon other multiple multicasting models. Given a number of multicast trees from source node to destination nodes using the multiple multicast trees, a probability of usage is calculated for each of the multicast trees with the highest probability for packet transmission assigned to the most efficient tree. Feedback is generated from destinations to source to provide the input for the probability calculations. For a given packet transmission, one tree will be chosen randomly based on the tree’s collective probability distribution and the packet will be sent on this tree. The trees’ probability distributions will be calculated and continually adjusted based on feedback of each tree’s performance. Packet transmission continues with periodic adjustment to the multicast tree usage probability based on multicast tree feedback measurements. It is the use of feedback and probability adjustments that makes PMT more efficient than other methods.
Advisors/Committee Members: Papachristou, Christou.
Subjects: Computer Engineering; Computer Science; Engineering
Keywords: Application Multicast; Feedback; Learned Path Selection
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13.
Kunaparaju, Keerthi.
VaROT: Methodology for Variation-Tolerant DSP Hardware Design using Post-Silicon Truncation of Operand Width.
Degree: MS, EECS - Computer Engineering, 2011, Case Western Reserve University
► Dramatic improvements in semiconductor integrated circuit technology presently make it possible to…
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▼ Dramatic improvements in semiconductor integrated circuit technology presently make it possible to integrate millions of transistors, onto a single semiconductor IC. These improvements in integration densities have been driven by aggressive scaling of technology, which has led to both increasing density and computing power. On the flip side, constant drive towards ever decreasing feature sizes has led to a signicant increase in manufacturing cost. One of the main causes of this increase in manufacturing cost is a signicant decrease in manufacturing yield due to manufacturing losses. These manufacturing losses are due to increasing process parameter variations that CMOS devices face at nanometer scale. Increasing device parameter variations in nanometer CMOS technologies cause large spread in circuit parameters such as delay and power, leading to parametric yield loss. For Digital Signal Processing (DSP) hardware, variations in circuit parameters can signicantly aect the Quality of Service (QoS). Post-silicon calibration and repair have emerged as an eective solution to maintain QoS in DSP chips under large process-induced parameter variations. However, existing calibration and repair approaches rely on adaptation of circuit operating parameters such as voltage, fre- quency or body bias and typically incur large delay or power overhead. In this thesis, a novel low-overhead approach of healing DSP chips by commensurately truncating the operand width based on their process shifts is presented. The proposed approach exploits the fact that critical timing paths in typical DSP datapaths originate from the least signicant bits. Hence, truncation of these bits, by setting them at constant values, can eectively reduce the delay of a unit, thereby avoiding delay failures. Efficient choice of truncation bits and values can minimize the impact of truncation on QoS. Appropriate design time modications including insertion of low-overhead truncation circuit and skewing the path delay distribution through gate sizing to maximize the delay improvement with truncation are presented. The proposed technique is applied on two common DSP circuits, namely Discrete Cosine Transform (DCT) and Finite Impulse Response (FIR). Simulation results show signicant decrease in critical path delay with the truncation of least signicant input bits and a graceful degradation in the QoS. Also there is a large improvement in manufacturing yield (41:6%) with up to 5X savings in power compared to existing approaches like voltage scaling and body biasing.
Advisors/Committee Members: Bhunia, Swarup.
Subjects: Electrical Engineering
Keywords: Post-Silicon Repair, DSP, Quality of Service, Operand Truncation, Yield Improvement
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14.
Lafrenz, Nicholas K.
Trojan Circuit Simulation and Evaluation.
Degree: MS, EECS - Computer Engineering, 2010, Case Western Reserve University
► This thesis introduces a purpose built simulator for the evaluation of Trojan…
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▼ This thesis introduces a purpose built simulator for the evaluation of Trojan circuit detection methods. Due to the increasing reliance of society and the government on integrated circuits and the increasing amount of outsourcing of the fabrication of said ICs, it has become necessary to be able to detect the presence of a Trojan circuit in a given IC. The simulator developed in this thesis uses the specific characteristics and necessities of the Trojan circuit detection problem and introduces a tool for use in evaluating these Trojan circuit detection techniques for accuracy and efficiency. Fault simulation techniques are utilized in novel ways to speed up Trojan circuit simulation, resulting in significant performance increases.
Advisors/Committee Members: Saab, Daniel.
Subjects: Computer science; Electrical engineering
Keywords: Trojan detection; Trojan simulation; circuit simulation
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15.
Leinweber, Lawrence.
Improved Cryptographic Processor Designs for Security in RFID and Other Ubiquitous Systems.
Degree: PhD, EECS - Computer Engineering, 2009, Case Western Reserve University
► In order to provide security in ubiquitous, passively powered systems, especially RFID…
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▼ In order to provide security in ubiquitous, passively powered systems, especially RFID tags in the supply chain, improved asymmetric key cryptographic processors are presented, tested and compared with others from the literature. The proposed processors show a 12%-20% area and a 31%-45% time improvement. A secure protocol is also presented to minimize cryptographic effort and communication between tag and reader. A set of power management techniques is also presented to match processor performance to available power, resulting in greater range and responsiveness of RFID tags.
Advisors/Committee Members: Papachristou, Christos.
Subjects: Computer science; Electrical engineering
Keywords: Cryptography, elliptic curve cryptography, power management, RFID, embedded systems
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16.
Marvel, Jeremy Alan.
Autonomous Learning for Robotic Assembly Applications.
Degree: PhD, EECS - Computer Engineering, 2010, Case Western Reserve University
► Robotic manipulators have been used to perform a myriad of repetitive industrial…
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▼ Robotic manipulators have been used to perform a myriad of repetitive industrial tasks with varying degrees of success and precision over the past several decades. Their use in mechanical assembly tasks, however, has been relatively minor due to both their limitations in classical position-control paradigms and the difficulty in algorithmically describing the process of assembly. Though the technology for sensing and compliantly adapting to physical contact has improved, robotic assembly solutions are still largely relegated to simple responsibilities such as peg-in-hole and rigidly fixtured configurations. This dissertation represents the progressive development and assessment of self-guided learning for model-assisted robotic assembly applications. Utilizing industrial manipulators outfitted with six-degree of freedom (DoF) force/torque sensors for compliant motion control, a method for self-optimization of assembly search parameters is developed that allows the robot to determine when its performance has improved using simple metrics of success. Based on prior experiences, the robot then generates internal representations—or models—of the assembly process in order to attempt to predict when certain parameter sequences are likely to result in superior assembly performances. This method is further augmented to algorithmically determine the quality and anticipated effectiveness of the models based on their profiles in the parameter-performance mapping space. Analysis of simulations with arbitrarily-large N-dimensional parameter spaces suggest that even relatively simple models are capable of abstracting useful information of assemblies, even in the presence of noise. These results were then corroborated by running physical trials with and without assistive models on a variety of automobile part assemblies.
Advisors/Committee Members: Newman, Wyatt.
Subjects: Artificial intelligence; Engineering; Robots
Keywords: Assembly, Machine Learning, Robot Learning
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17.
Nagubadi, Vivek.
Extraction Based Verification Method For Off The Shelf Integrated Circuits.
Degree: MS, EECS - Computer Engineering, 2010, Case Western Reserve University
► Off-the-shelf Integrated Circuits (ICs) are used in the design of many products.…
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▼ Off-the-shelf Integrated Circuits (ICs) are used in the design of many products. The IC is supposed to implement a set of available specifications describing the function of the IC. Users of off-the-shelf ICs need a simple and effective method to validate the specifications to insure that the IC implements exclusively the set of available specifications. In this thesis, we propose an approach to validate these specifications by a set of IC re-engineering experiments. The proposed approach is based on the construction of a high-level description of the packaged IC and on using the extracted description to validate the specifications. The approach uses the scan operations (available for manufacturing test of the IC) and the IC specification to disassemble the states/flip-flops and output functions of the packaged IC. Using the disassembled functions, a Register Transfer Level (RTL) model suitable for Computer-Aided Design manipulation is constructed. The disassembling is based on an ATPG scan experiment. Information on the scan chains is employed to construct the connectivity of the logic function. The connectivity is then used to discover the implemented logic. Using the proposed approach, we re-constructed over 90% of the system functions for an example IC. Scope for future work has been discussed at the end of the thesis work.
Advisors/Committee Members: Saab, Daniel.
Subjects: Engineering
Keywords: CIRCUITS; Reverse Engineering; speciï¬cations; flip-flops; y2; Y0; netlist
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18.
Narasimhan, Seetharam.
Ultralow-Power and Robust Implantable Neural Interfaces: An Algorithm-Architecture-Circuit Co-Design Approach.
Degree: PhD, EECS - Computer Engineering, 2012, Case Western Reserve University
► Implantable systems are used in various contexts for interfacing with the body…
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▼ Implantable systems are used in various contexts for interfacing with the body and for providing real-time monitoring and control capability. In particular, implantable neural interfaces can be used to radically improve our understanding of the nervous system and to provide precise treatments for a variety of neurological problems. However, these systems require significant computing power to perform real-time in-situ analysis of neural signals to recognize behaviorally meaningful patterns which are used to trigger appropriate corrective actions. Due to the tight area and power constraints of neural implants, it is important to develop novel algorithm-architecture-circuit co-design approaches for efficient implementation of neural signal analysis. First, we develop an algorithmic framework which is suitable for ultralow-power hardware implementation while simultaneously satisfying emerging design requirements like reliability and security. The algorithm is based on building a dynamic hierarchical multi-level vocabulary of neural patterns in the wavelet domain. The vocabulary-based analysis allows recognition of neural patterns at multiple levels (spike, burst, and pattern of bursts across multiple channels) and transmission of recorded data with large compression, thus, saving power and communication bandwidth of the integrated telemetry device. Hardware implementation of the proposed algorithm aims at reducing system power through choice of appropriate architecture and circuit-level design techniques. We show that a super-threshold design operating at a much higher frequency can achieve comparable energy dissipation as a sub-threshold low-frequency design through application of extensive power gating. It also provides significantly higher robustness of operation and yield under large process variations. We propose an architecture-level preferential design approach for further energy reduction at the cost of graceful degradation in output signal quality under voltage scaling and parameter variations. Considering the emerging need of secure computing in implantable systems, we analyze the various security threats in the proposed system. We exploit the vocabulary-based encoding of neural signals to realize an ultra-lightweight data obfuscation solution. Furthermore, we consider an emerging security threat namely, hardware Trojan attack, where an adversary introduces malicious modifications of a circuit during design or fabrication. We analyze the effectiveness of different Trojan attacks in implantable systems and develop side-channel analysis based Trojan detection approaches.
Advisors/Committee Members: Bhunia, Swarup.
Subjects: Biomedical Engineering; Computer Engineering
Keywords: Implantable Electronics, Neural Interface Systems, Vocabulary-based Approach, Preferential Design, Algorithm-Architecture-Circuit Co-design, Security, Hardware Trojan
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19.
Paul, Somnath.
Computing with Memory for Energy-Efficient Robust Systems.
Degree: PhD, EECS - Computer Engineering, 2011, Case Western Reserve University
► Reconfigurable computing platforms that offer the flexibility to configure hardware resources according…
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▼ Reconfigurable computing platforms that offer the flexibility to configure hardware resources according to application requirements, provide great opportunity to accelerate wide variety of applications. Over the past decade, Field Programmable Gate Arrays (FPGAs) have grown to be the most popular hardware reconfigurable computing platform. Modern FPGAs integrate an array of spatially distributed logic/memory blocks and programmable routing resources. Such a framework can provide several orders of magnitude more throughput compared to conventional microprocessor based designs. The power and performance of conventional FPGA platform is largely dominated by programmable interconnects, which have poor technological scalability. Moreover, the performance improvement for applications mapped to the FPGA platform is largely limited by the off-chip bandwidth. A reconfigurable framework which minimizes the contribution from the programmable interconnects and mitigates the bandwidth bottleneck by moving the computing engine close to the data is expected to significantly improve the energy efficiency of reconfigurable systems. In this work, we propose a novel hardware reconfigurable framework, referred to as memory based computing (MBC) framework. The main computing fabric for such a framework is a 2-D memory array which is used to store the functional behavior for the mapped application. Each computing element in the framework is temporal in nature and an array of these elements is used to map an application in a spatio-temporal fashion. Temporal execution inside each compute element reduces the requirement for programmable interconnects, thus improving the energy-efficiency over a fully spatial reconfigurable framework. In addition to storing the functional behavior, the memory arrays also store data, thus mitigating the off-chip bandwidth bottleneck. The framework is particularly appealing for system design with many emerging non-silicon nano-devices, which are amenable to dense, regular nonvolatile memory design. With the primary computing fabric being memory, the proposed MBC framework can be made robust to high device failure rates at nanoscale technologies. We have developed architecture and circuit level optimization techniques for the proposed framework along with efficient algorithms for automatic mapping of applications to this framework. Finally, we have investigated application of this framework as a reconfigurable computing resource in a processor for reliability improvement and hardware acceleration.
Advisors/Committee Members: Bhunia, Swarup.
Subjects: Computer Engineering
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20.
Reddy, Nitin.
DRIVER ASSISTANCE FOR ENHANCED ROAD SAFETY AND TRAFFIC MANAGEMENT.
Degree: MS, EECS - Computer Engineering, 2009, Case Western Reserve University
► This study explores the use of inter vehicle communication to enhance road…
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▼ This study explores the use of inter vehicle communication to enhance road safety andtraffic management. A vehicle’s engine control unit (ECU) manages and controls various sensor signals, inputs and determines the output in terms of torque, fuel quantity and actuator positions. The data available in the ECU is however restricted only to that particular vehicle where it was generated. This work presents a scenario where critical data from each vehicle is broadcasted and a dynamic ad-hoc network of vehicles is formed. The algorithms in the ECU then detect possible collisions, decides which vehicle should take action and alerts the driver with the most optimum resolution. The analysis presented here is based on simulation data. Traffic management is achieved with modules placed along the road, which collect the broadcasted data. Modules, after analyzing traffic density and average speeds, interact with neighboring modules. This traffic information is broadcasted to all vehicles in close proximity to the traffic modules. The vehicle uses this information along with details from the navigation system to reroute the automobile to avoid high traffic areas.
Advisors/Committee Members: Papachristou, Christos.
Subjects: Computer science
Keywords: traffic management, collision avoidance, car safety, embedded systems, driver assistance
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21.
Renfrew, Mark E.
A Comparison of Signal Processing and Classification Methods for Brain-Computer Interface.
Degree: MS, EECS - Computer Engineering, 2009, Case Western Reserve University
► Non-invasive Brain-Computer Interface (BCI) methods have been investigated for use in physical…
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▼ Non-invasive Brain-Computer Interface (BCI) methods have been investigated for use in physical therapy of stroke patients with motor deficits. This study investigates several methods of feature extraction and classification for suitability for use in such therapy. Electroencephalographic (EEG) data were collected during a motor task from four healthy control subjects and three subjects with motor deficiencies resulting from stroke. The EEG data were filtered using autoregressive (AR), mu-matched, and wavelet decomposition (WD) methods. The filtered data were classified using Support Vector Machines (SVM) and a linear classifier. Wavelet filtering showed a statistically significant (p < 0:05) improvement in classification accuracy over AR filtering for one subject when using the linear classifier. SVMs showed a statistically significant improvement over the linear classifier for all filtering methods for three subjects. No difference in classification accuracy was seen between linear and nonlinear SVMs.
Advisors/Committee Members: Cavusoglu, M. Cenk.
Subjects: Biomedical research; Electrical engineering
Keywords: EEG; electroencephalography; BCI; brain-computer interface; wavelets; discrete wavelet transform; autoregressive; support vector machines
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22.
Shewinvanakitkul, Prapan.
An Item Response Theory Framework for Combined Ability Estimation and Question/Hint Selection.
Degree: MS, EECS - Computer Engineering, 2012, Case Western Reserve University
► This study examines a new approach to the combined problem of question…
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▼ This study examines a new approach to the combined problem of question parameter/examinee ability estimation and examinee learning in an analytical framework using computerized adaptive testing (CAT), item response theory (IRT), and adaptive learning. We investigate how to estimate examinee ability coupled with how to increase examinee learning by providing suitably chosen hints to arrive at a learning goal. The overall objective is to increase examinee ability with the minimum number of questions and hints in an adaptive testing framework. Monte Carlo simulation experiments are conducted in order to validate the model and test algorithm performance. Results show that estimated examinee abilities are increased to specified set points by providing suitably chosen number of appropriate hints.
Advisors/Committee Members: Buchner, Marc.
Subjects: Educational Technology; Educational Tests and Measurements
Keywords: Inteligence tutoring system
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23.
Shiyanovskii, Yuriy.
Reliability of SRAMs and 3D TSV ICS: Design Protection from Soft Errors and 3D Thermal Modeling.
Degree: PhD, EECS - Computer Engineering, 2012, Case Western Reserve University
► With CMOS technology scaling into deep nanoscale level, reliability issues have emerged…
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▼ With CMOS technology scaling into deep nanoscale level, reliability issues have emerged as key concerns for SRAM memories. The reliability of SRAM memories is critical for the overall reliability of the modern ICs because memories occupy a large portion of the chip area. SRAM memory susceptibility to soft errors caused by ionizing particles significantly increases due to small node capacitance. Further aggressive technology scaling is reaching its saturation due to limitations posed by physics on transistor size reduction. Emerging 3D through-silicon vias (TSV) chip integration can provide an alternative solution to satisfy ever-growing demands for packing density. However, increased heat generation per unit footprint and poor heat dissipation in 3D stacks can lead to high chip temperatures, thus thermal management is considered one of the most critical reliability issues in 3D ICs. This work addresses the most urgent reliability concerns in conventional SRAM memories caused by soft errors and in emerging 3D TSV ICs caused by excessive heat generation, respectively. In this research, a new methodology based on functional component separation, for the design of soft error tolerant SRAM cells, is presented. The methodology is applied to develop several novel SRAM cell designs with improved soft error tolerance. Novel hardened SRAM cell designs using on-demand protective capacitor circuitry and tri-state inverters are developed based on the proposed methodology of functional separation. The developed SRAM designs offer high soft error protection level. In addition to soft error robustness, the tri-state based SRAM cells demonstrate excellent write performance, low power consumption, and high read cell stability, and are scalable into the deep nanoscale region. A new 3D analytical thermal model is developed to simulate temperature fields in 3D TSV ICs. The model allows for consideration of inhomogeneous localized heating sources, heat exchange within the layer, heat transfer through external surfaces of the device, inter-layer heat transfer with possible inhomogeneous TSV placement, and micro-channel cooling. The model is applied to analyze the steady state thermal behavior of 3D TSV devices with inhomogeneous power densities. The model has a high computational efficiency, and allows simulations to be performed in real time.
Advisors/Committee Members: Papachristou, Christou.
Subjects: Computer Engineering; Electrical Engineering
Keywords: Soft Error; SRAMs; Hardening; Reliability; Memory Cell Design; 3D ICs; TSV; Through-Silicon Vias; Thermal Modeling; Thermal Management
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24.
Sirigiri, Vijay Krishna.
Ultra-Low Power Ultra-Fast Hybrid CNEMS-CMOS FPGAs.
Degree: MS, EECS - Computer Engineering, 2011, Case Western Reserve University
► Designing energy efficient FPGAs have been the focal point of contemporary research…
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▼ Designing energy efficient FPGAs have been the focal point of contemporary research work which extends their horizon to battery supported devices facilitating increased battery life and reduced costs of cooling. This research proposes novel Hybrid CNEMS-CMOS FPGAs which consists of routing switch blocks made up of CNEMS. Complimentary Nano Electro Mechanical Switch (CNEMS), a manufactured switch, operates around 1V, possess zero leakage current, zero parasitic capacitance, low ON resistance and > 1 GHz resonating frequency. Hybrid architectures offers 1) reduced routing leakage power consumption because of zero leakage of CNEMS, 2) improved critical path delay since CNEMS has order of magnitude less ’ON’ resistance when compared to CMOS. CNEMS in this environment is used only during configuration which enables to overcome the speed degradation caused by the mechanical movement. CNEM based FPGA switch blocks facilitates higher integration density as they do not need SRAM cells for storing the configuration information.
Advisors/Committee Members: Saab, Daniel.
Subjects: Computer Engineering
Keywords: Hybrid FPGA; CNEMS; Switch Blocks
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25.
Stalter, David T.
Digital Logic and Multi-valued Memory Using NEMS Switches.
Degree: MS, EECS - Computer Engineering, 2010, Case Western Reserve University
► Nano-electromechanical systems (NEMS) switches provide a promising alternative to conventional CMOS technology…
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▼ Nano-electromechanical systems (NEMS) switches provide a promising alternative to conventional CMOS technology in terms of building digital circuits. These switches can theoretically operate at much lower power and in extremely harsh environments (in terms of temperature and radiation) where conventional CMOS technology fails to work reliably. Digital circuit design using NEMS technology can utilize innovative switch structures due to the freedom offered by the three-dimensional mechanical structure and a diverse set of materials. Silicon carbide (SiC) is a promising material for NEMS switch design due to its electrical conductivity and ability to operate in harsh environments such as space shuttle and combustion engine. In this work, novel NEMS structures for SiC are explored in two different areas: multiplexing and multi-valued memory cells. In each scenario, multiple alternative designs are developed, verified through electrical and mechanical analysis, and compared in terms of multiple design metrics. For each structure, an appropriate circuit-compatible model is developed and electrically simulated. Mathematical analysis is performed to predict the behavior of each design. The simulation results confirm correct functional behavior and provide estimates on switching parameters.
Advisors/Committee Members: Bhunia, Swarup.
Subjects: Electrical engineering
Keywords: MEMS; NEMS; multivalue memory; cantilever; digital logic; harsh environment
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26.
Thorndike, David Andrew.
A Multicore Computing Platform for Benchmarking Dynamic Partial Reconfiguration Based Designs.
Degree: MS, EECS - Computer Engineering, 2012, Case Western Reserve University
► With the increasing application of multiple processor cores (multicores) within embedded system…
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▼ With the increasing application of multiple processor cores (multicores) within embedded system applications, as well as the pervasive utilization of the field-programmable gate array (FPGA), the embedded system development community has been exploring the advantages of the dynamically reconfigurable nature of FPGAs. Given size and power limitations, a primary motivation for this interest is to enable dynamic customization of hardware to optimize system performance for the various algorithms that a system encounters. This work presents a hardware based platform for studying dynamic reconfiguration of FPGAs in the context of multicore embedded systems. It also presents a methodology for developing the hardware and software for these systems. An important aspect of this work was to maximize the utilization of open source hardware and software intellectual property (IP). An example of the basic implementation flow is also provided, along with some benchmarking results.
Advisors/Committee Members: Papachristou, Chritos.
Keywords: multicore; reconfigurable computing; multicore reconfigurable computing platform; DPR
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27.
Wang, Lei.
Fine-Grained Width-Aware Dynamic Supply Gating for Active Power Reduction.
Degree: MS, EECS - Computer Engineering, 2012, Case Western Reserve University
► As technology scales down, leakage power is becoming more dominant in total…
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▼ As technology scales down, leakage power is becoming more dominant in total active power. This trend makes run-time leakage control an important concern in today's integrated circuit (IC) design. Hence, a design approach that allows dynamic leakage reduction in circuit blocks at low overhead can provide an attractive solution. In this work, a novel width-aware fine-grained dynamic supply gating (WADSG) technique is proposed to reduce both leakage and redundant switching power in processor datapath and caches. WADSG exploits the abundance of narrow-width (NW) operands in general-purpose and embedded application to "supply-gate" unused parts of integer execution units and memory blocks at run-time. On circuit level, a novel levelized supply gating strategy is developed to eliminate the wake-up delay overhead. We employ the WADSG approach to a superscalar processor. To minimize the wake-up power, we use a width-aware instruction issue policy. For the L1 and L2 cache, we store the width information per "ways" of associate cache and supply-gate the most significant bits of the NW ways. A width-aware block allocation and replacement policy is also proposed to maximize the number of NW ways. Simulation results for 45nm technology with Spec2k benchmarks show major savings (34.5%) in total processor power (considering both switching and active leakage power) with negligible performance impact. Layout of supply gated design for both datapath and memory units are done, and post-layout simulation are also performed with TSMC 250nm technology to validate the proposed design approach.
Advisors/Committee Members: Bhunia, Swarup.
Subjects: Computer Engineering
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28.
Warren, Emily Amanda.
Machine Learning for Road Following by Autonomous Mobile Robots.
Degree: MS, EECS - Computer Engineering, 2008, Case Western Reserve University
► This thesis explores the use of machine learning in the context of…
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▼ This thesis explores the use of machine learning in the context of autonomous mobile robots driving on roads, with the focus on improving the robot's internal map. Early chapters cover the mapping efforts of DEXTER, Team Case's entry in the 2007 DARPA Urban Challenge. Competent driving may include the use of a priori information, such as road maps, and online sensory information, including vehicle position and orientation estimates in absolute coordinates as well as error coordinates relative to a sensed road. An algorithm may select the best of these typically flawed sources, or more robustly, use all flawed sources to improve an uncertain world map, both globally in terms of registration corrections and locally in terms of improving knowledge of obscured roads. It is shown how unsupervised learning can be used to train recognition of sensor credibility in a manner applicable to optimal data fusion.
Advisors/Committee Members: Newman, Wyatt.
Subjects: Computer science; Engineering; Robots
Keywords: machine learning; autonomous robot; driving; Urban Challenge; sensor fusion; unsupervised learning; global map; road following
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29.
Yang, Lan.
An Area-Efficient Architecture for the Implementation of LDPC Decoder.
Degree: MS, EECS - Computer Engineering, 2011, Case Western Reserve University
► Due to its near Shannon limit performance in high speed communication, low-density…
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▼ Due to its near Shannon limit performance in high speed communication, low-density parity check (LDPC) code has performed a strong comeback recent years. In this work, a partial parallel decoding architecture is proposed based on a column-layered LDPC decoding scheme [2]. The purpose of this work is to make a tradeoff between area cost and throughput. I construct the structure of the partial parallel decoder, and compare its throughput and area cost with the design in [2]. Then I obtain the synthesis results of my design with Xilinx FPGA tool. The device utilization summary and timing summary are provided at the end of this work. Comparing with the design in [2], the partial parallel design in my work needs much less hardware resources. As a result, when the area is limit and a lower throughput is acceptable, my design can be considered instead of the design in [2].
Advisors/Committee Members: Zhang, Xinmiao.
Subjects: Computer Engineering
Keywords: Low-density parity-check (LDPC) codes, Partial parallel, Error Correcting Code Decoder, FPGA implementation
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30.
Yanick, Anthony Joseph.
Driving By Speaking: Capabilities and Requirements of a Vocal Joystick.
Degree: MS, EECS - Computer Engineering, 2012, Case Western Reserve University
► This thesis presents an investigation of prospects for driving a mobile robot…
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▼ This thesis presents an investigation of prospects for driving a mobile robot or wheelchair with vocal commands. It is shown that latencies can degrade driving performance, which limits vocal commands to brief utterances. To command degrees of intensity of commands, such as curvature of turns, without benefit of multi-word expressions, it may be possible to encode additional information in prosodic features. Experimental results are presented indicating that prosody can be used to improve performance of a vocal interface. Prosodic features of rhythm, pitch and volume are examined to interpret how subjects use prosody to enhance driving commands, leading to suggestions of how to design a computer interface that exploits prosody.
Advisors/Committee Members: Newman, Wyatt.
Subjects: Computer Engineering
Keywords: Prosody, Mobile Robotics, Robotic Control, Semiotics, Cognitive Science
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