Department: Computer Engineering ![[clear]](close-x.png "Remove this limiter")
42 matches in the database.
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1.
Afifi, Faten Helmy.
Detecting errors in nonlinear functions for computer software.
Degree: PhD, Computer Engineering, 1992, Case Western Reserve University
► In this research a new approach is proposed to select test data…
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▼ In this research a new approach is proposed to select test data for testing nonlinear functions in computer programs, with only a small additional cost and effort beyond that required for linear functions. This approach is applied to a function used for control flow, such as a predicate inequality or equality constraint, as well as to a function given as an input-output relationship. In this approach, we will obtain test data to detect linear errors in the given nonlinear function. An error-space criterion previously given by Zeil will be utilized. A necessary and sufficient condition for the test data will be specified to guarantee the satisfaction of this criterion. This leads to a simple, practical and efficient method to select test data which satisfies that condition. The advantage of this approach is that the number of test points is about the same as required for comparable linear functions and these test points are very effective in detecting nonlinear errors as well. Our approach shows that, no more than (n + 2) test points are required for the criterion to be satisfied, where n is the number of input variables. A simple extension will be proposed, for the equality case, to detect any error in the nonlinear function; the number of test points required is (n + m + 1), where m is the number of nonlinear terms. The condition that these test points must satisfy will be given. An analysis will also be given to show that the test points chosen according to this simple approach is a very effective subset of a set of test points that can be used to detect any error that could occur in nonlinear functions
Advisors/Committee Members: White, Lee J.
Subjects: Computer Science
Keywords: Computer software; Nonlinear functions errors
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2.
Akbari, Kazem.
A new neurocomputing approach: Software and hardware designs.
Degree: PhD, Computer Engineering, 1995, Case Western Reserve University
► This study also presents a new approach for both software and hardware…
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▼ This study also presents a new approach for both software and hardware designs of neural networks. The software design of this work presents a new scheduling approach based upon a deterministic modified Hopfield model to solve "File-Transfer" scheduling, an NP-Complete constraint satisfaction problem. The proposed model is mapped onto a two-dimensional neural architecture for the transfer scheduling of files between various nodes of a network, by which the overall transfer times should be minimized. Neural Network-based Scheduling is achieved by formulating the scheduling problem in terms of energy function and by using the "Motion Equation" corresponding to the variation of energy levels. The main contribution of this part is an efficient parallel algorithm under time and resource constraints appropriate for implementing on parallel machines. Another quite important contribution of this part is applying a novel technique which considerably improves the performance and efficacy of the system. However, neurons' motion equation is the core of this guided movement mechanism and guarantees that the state of system mostly converges to the optimal state. This part was modeled and simulated in C language successfully. The second part of this work presents a developmental appro ach for hardware implementation of neural networks. The primary goal of this part is to construct a general purpose neural system, comprising sufficient neural processors and powerful enough for mapping and testing various neural algorithms and hypothesis. To do this, first a new multipurpose neurocomputing system is proposed (an SIMD machine), and then on the basis of the proposed system a neural network architectural representation is provided for the mapping and testing of Artificial Neural Network (ANN) algorithms, modeled behaviorally using the VHSIC Hardware Description Language (VHDL). Due to some major impediments in construction of ANN chips, VHDL design entities and configurations were applied to neural network algorithm and simulation, to model, test, and verify both circuit and algorithm in the same VHDL representation. After all testings and simulations confirmed the capability and correctness of the system, the proposed system is prepared for the fabrication processes using "Compass Synthesizer tools" to create the corresponding layouts.
Advisors/Committee Members: Papachristou, Christos A.
Keywords: neurocomputing Software hardware designs
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3.
Al-Hammouri, Ahmad Tawfiq.
INTERNET CONGESTION CONTROL: COMPLETE STABILITY REGION FOR PI AQM AND BANDWIDTH ALLOCATION IN NETWORKED CONTROL.
Degree: PhD, Computer Engineering, 2008, Case Western Reserve University
► The Internet represents a shared resource, wherein users contend for the finite…
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▼ The Internet represents a shared resource, wherein users contend for the finite network bandwidth. Contention among independent user demands can result in congestion, which, in turn, leads to long queueing delays, packet losses or both. Congestion control regulates the rate at which traffic sources inject packets into a network to ensure high bandwidth utilization while avoiding network congestion. In this thesis, we present contributions pertaining to two specific areas in the Internet congestion control: PI AQM and bandwidth allocation in Cyber-Physical Systems (CPSs). In the area of PI AQM, we present an analytic derivation of the complete stability region. The stability region represents the entire set of the feasible design parameters that stabilize the closed-loop TCP-AQM system. Utilizing the complete stability region, we show that the PI parameters used in the literature can be excessively conservative. We also show that provably stable controller parameters can exhibit widely different levels of performance. Furthermore, we present examples of PI controllers that are stable and have significantly better performance than previously proposed ones. These facts explain the previous observation about PI sluggish responsiveness and stress the importance of obtaining the complete stability region for the PI AQM. As for CPSs bandwidth allocation, we devise a bandwidth allocation scheme for Cyber-Physical Systems that have their control loops closed over a distributed network. We formulate the bandwidth allocation as a convex optimization problem. We then present an allocation scheme that solves this optimization problem in a fully distributed manner. In addition to being fully distributed, the proposed scheme is asynchronous, scalable, dynamic and flexible. Furthermore, we design robust and resilient queue controllers to enhance the performance of the bandwidth allocation scheme to better fulfill the requirements of the CPSs control loops. Throughout the thesis, we present analytical results and we validate them with packet-level simulations via ns-2.
Advisors/Committee Members: Liberatore, Vincenzo.
Subjects: Computer Science
Keywords: Sensor-Actuator networks; SANETs; Active Queue Management; Time-delay systems; Steady-state backlogs; Utility functions; Cyber-Physical Systems; Networked control systems; Queue controller
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4.
Chen, Bainan.
Hardware Implementation of Error Control Decoders.
Degree: MS, Computer Engineering, 2008, Case Western Reserve University
► In this thesis, an FPGA implementation of a factorization processor for algebraic…
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▼ In this thesis, an FPGA implementation of a factorization processor for algebraic soft-decision Reed-Solomon (RS) decoding is first presented. The design is based on the root-order prediction architecture and extensible for the factorization of polynomials with designated degrees. Parallel processing is exploited to speed up the polynomial updating involved in the factorization. To resolve the data dependency issue in parallel polynomial updating, an efficient coefficient storage and transfer scheme with small memory requirement and low latency is proposed. Synthesis results show that the factorization processor for a (255, 239) RS code with maximum multiplicity four can achieve an average decoding speed of 226 Mbps on a Xilinx Virtex-II FPGA device when the frame error rate is less than 10-2.Next, an FPGA implementation of a factorization processor for algebraic soft-decision bit-level generalized minimum distance (BGMD) RS decoding is presented. The BGMD factorization processor utilizes a low-latency and prediction-free scheme for root computation. Furthermore, parallel processing architectures and efficient coefficient storage schemes are employed to reduce the latency. Synthesis results show that the BGMD factorization processor for a (255, 239) RS code with maximum multiplicity two can achieve a decoding speed of 815 Mbps on a Xilinx Virtex-II FPGA device. Prior research efforts have been focusing on using BCH codes for error correction in multi-level cell (MLC) NAND flash memory. However, BCH codes often require highly parallel implementations to meet the throughput requirement. As a result, large area is needed. In this thesis, RS codes are proposed to be used for the error correction inMLC flash memory. A (828, 820) RS code has almost the same rate and length in terms of bits as a BCH (8248, 8192) code. Moreover, it has at least the same error-correcting performance in flash memory applications. Nevertheless, with 70% of the area, the RS decoder can achieve a throughput that is 121% higher than the BCH decoder. A novel bit mapping scheme using Gray code is also proposed. Compared to direct bit mapping, the proposed scheme can achieve 0.02 dB and 0.2dB additional gains by using RS and BCH codes, respectively, without any overhead.
Advisors/Committee Members: Zhang, Xinmiao.
Subjects: Electrical engineering
Keywords: Reed-Solomon codes; factorization; algebraic soft-decision decoding; BCH codes; VLSI architecture; flash memory
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5.
Chen, Pu.
ATT: Execution models for logic programs.
Degree: PhD, Computer Engineering, 1995, Case Western Reserve University
► Logic programs, which are represented by well motivated logical formalisms, can be…
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▼ Logic programs, which are represented by well motivated logical formalisms, can be viewed operationally as the execution of an abstract computation model on a logical theory, guided by some control information supplied with the theory. This model is then viewed as a goal-driven controlled reduction from the logical formalism of the program. The original goal reduction rules give considerable freedom to specify control information for selecting which goal to reduce and for selecting which logical formalism to apply to the goal. A number of control strategies have been investigated, resulting in a number of logic programming languages. In order to design general purpose execution models to support a number of control strategies in different logic programming languages, a multi-layer hierarchical structure of execution models should be employed. In such a hierarchy, the uppermost layer is an abstract execution model developed to support the computation of logic programs. The middle layer, a process network model, is constructed to support the abstract execution model. An abstract machine is at the bottom of the hierarchy to support the process network model. An important problem in parallel computation is to decompose computation into modules. Parallelism could be exploited at each layer of the hierarchical structure of execution models for logic programs. The common forms of parallelism in most parallel execution models for logic programs are AND-parallelism and OR-parallelism, and these can be explicitly expressed in logic programs. Operational parallelism, which may or may not be explicitly expressed in logic programs, could be exploited by extracting operational information from the control strategies of goal reductions. Once operations in the computation are classified, different types of operations could be assigned to different processes in the execution models of logic programs. Operational parallelism could be achieved by executing these processes simultaneously. However, for some reasons, operational parallelism has not been given much attention by researchers The objectives of this research are to exploit operational parallelism in the computation of logic programs and to construct a general purpose hierarchical structure of execution models which support several logic programming languages. This dissertation designs a three layer hierarchical structure of execution models for logic programs, which I have called ATT. This execution model hierarchy has its roots in PR/T net for the abstract execution model and in Warren Abstract Machine for the abstract machine model respectively. The ATT system offers several features: It employs concurrent execution models, supports both Don't know nondeterminism and Don't care nondeterminism. It can also be extended to distributed computing environments. In order to demonstrate the ideas on a shared memory machine, I implemented a prototype abstract machine in the C programming language, which supports committed-choice logic programming languages
Advisors/Committee Members: Sterling, Leon S.
Subjects: Computer Science
Keywords: Logic programs; Execution models
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6.
Chiu, Shu-Kau.
A methodology for integrating design and test at the system level.
Degree: PhD, Computer Engineering, 1992, Case Western Reserve University
► Recent progress of high level synthesis has illuminated an effective aid for…
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▼ Recent progress of high level synthesis has illuminated an effective aid for system designers. However, to produce a high quality design, there is a need to consider design for testability (DFT) during the synthesis process. Motivated by this requirement, a methodology is presented in this thesis to cover the gap between design and test at the system level. Following this methodology, two approaches – heuristic and integer linear programming – are given to analyze the testability for large or small systems, respectively. Applying to a Built-In Self-Testing technique, the heuristic approach is shown to be fast and effective on benchmark circuits. Demonstrated with an application to the Symbolic Test Pattern Generation Technique, the integer programming approach is promising for reasonable-sized circuits. Incorporation of the heuristic approach into an experimental high level synthesis system, SYNTEST, has been completed with the overall objective of generating testable designs at the register transfer level.
Advisors/Committee Members: Papachristou, Christos A.
Subjects: Computer Science
Keywords: integrating design; system level
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7.
Ding, Chen.
Computer formal drawings and their automation.
Degree: PhD, Computer Engineering, 1991, Case Western Reserve University
► Pictures are an important communication medium; but generating pictures in a computer…
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▼ Pictures are an important communication medium; but generating pictures in a computer system is tedious and time consuming. Besides, many other problems are found in using pictures. Our work aims to (1) develop models to formalize the objects to be visualized and the pictures that visualize them, (2) use visualization schemes to solve the automatic visualization problem, (3) use aesthetics rules to solve the aesthetics problem, and (4) build a system to automate the process of generating computer drawings. We have developed the Formal Drawing Model which formalizes computer drawings without losing visual reality. Elements in the Formal Drawing Model possess formal syntax and semantics. The model is powerful enough to accommodate a large variety of computer drawings. Aesthetics has not been addressed adequately in the past. In our work, we examine in detail what makes a picture pleasing and the mechanisms affecting the efficiency of using pictures to convey information. Aesthetics rules, distilled from numerous diagram drawings in textbooks, are the key component in the automatic drawing system proposed. Based on our theoretical work, we build a framework to automate diagram drawing. We stress four issues which are critical to such a system but have not been integrated in the past. They are (1) Appropriate user involvement, (2) User custom ization, (3) Efficiency, and (4) Aesthetics. Solving these problems will allow us to build a more powerful and natural automatic drawing system. ftn*Work supported by K. C. Wong Educational Foundation, Hong Kon.
Advisors/Committee Members: Mateti, Prabhaker.
Subjects: Computer Science
Keywords: Computer formal drawings automation
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8.
Du, Kaizheng.
On automated query modification techniques for databases.
Degree: PhD, Computer Engineering, 1993, Case Western Reserve University
► In many cases, in order to satisfy certain constraints specified in…
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▼ In many cases, in order to satisfy certain constraints specified in a database query, the query needs to be modified. However, users' "manual" modification is an extra burden on users and, sometimes, may not be correct when users lack knowledge about the database. In a real-time environment, users' manual modification may be too slow to make a query satisfy a given time dead-line. In this thesis, a general automated database query modification model is proposed for automatically modifying database queries with constraints. Five types of query modification constraints, namely, time constraints, error constraints, aggregate function constraints, PCF constraints and count proportionality constraints are introduced. To enable query modification to be performed automatically, two query modification protocols, namely, the use of superset/subset chains based on relation fragmentation and the use of sampling data, are specified. Based on the two query modification protocols, a detailed query modification mechanism for enforcing time and error constraints are given. An iterative query evaluation technique is used to process nonperiodically occurring queries with time constraints. An incremental query evaluation technique is used to process periodically occurring queries with time constraints. Error removal and error estimation techniques are introduced to enforce error constraints. Finally, extending the above listed techniques into enforcing the remaining three types of constraints is briefly summarized. In this thesis, query estimation techniques for aggregate relational algebra queries COUNT, SUM and AVERAGE are also presented. Two statistical estimators, the Jackknife estimator and the Chao's estimator, for COUNT queries with projection are used. Estimators using double sampling technique for SUM and AVERAGE queries are introduced, and new sampling plans based on systematic sampling and stratified sampling to increase the estimation accuracy are investigated. These new estimators and sampling plans are extensively used in automated query modification. Some of the techniques and associated algorithms proposed in this thesis have been implemented in CASE-DB, which is a prototype relational database management system developed at Case Western Reserve University.
Advisors/Committee Members: Ozsoyoglu, Gultekin.
Keywords: automated query modification; databases
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9.
Gajurel, Sanjaya.
Multi-Criteria Direction Antenna Multi-Path Location Aware Routing Protocol for Mobile Ad Hoc Networks.
Degree: PhD, Computer Engineering, 2008, Case Western Reserve University
► In this paper, I develop Directional Antenna Multi-path Location Aware Routing (DA-MLAR)…
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▼ In this paper, I develop Directional Antenna Multi-path Location Aware Routing (DA-MLAR) that is a location aware routing with directional antenna capability. DA-MLAR is a reactive routing protocol that minimizes the protocol overhead of other reactive routing protocols. DA-MLAR also improves the packet delivery ratio and end-to-end delay. The long radio transmission range obtained using directional antenna can decrease the number of network partitions there by reducing the number of rebroadcasts. It also reduces the number of routing hops. The directionality further reduces the network interferences by directing the beam only towards the receiving node and involving few intermediate nodes that are in the direction of receiving node. Two extensions of DA-MLAR - DA-MLAR with on demand adjustment of transmission power (DA-MLAR-ODTP) and beam width (DA-MLAR-ODBW) are proposed which further improves the performance metrics of ad hoc networks. In the first phase, the adjustment is made based on the calculated distance between the current sending node and the receiving node in the network. In the second phase, the adjustment also incorporates the effect of random Received Signal Strength (RSS) environment. Multi-objective approach is adopted to assess the network performance of MANET with complex, competing and conflicting objectives – maximizing packet delivery ratio, minimizing protocol overhead, and minimizing energy consumption. The preference of objectives depends on the type of application. In space, energy consumption is given more preference than other objectives. I have used the Normalized Weighted Additive Utility Function (NWAUF) approach to obtain the best alternatives. Through simulations using ns-2, I have demonstrated that DA-MLAR exhibits better network performance. Some performance metrics like packet delivery ratio and end-to-end delay have been significantly improved using DA-MLAR-ODTP and DA-MLAR-ODBW with check in protocol overhead and energy consumption. Subsequent simulation analysis using ns-2 is provided.
Advisors/Committee Members: Malakooti, Behnam.
Keywords: Ad Hoc Network; Directional Antenna; Location Aware Routing Protocol; Mobile Ad-hoc Network; Network Performance Computation and Evaluation; On Demand Routing; Beam Width adjustment; Transmission power adjustment; Multi-objective Analysis
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10.
Gill, Balkaran S.
Design and Analysis Methodologies to Reduce Soft Errors in nanometer VLSI Circuits.
Degree: PhD, Computer Engineering, 2006, Case Western Reserve University
► As process technology advances into Very Deep Sub-Micron (VDSM) level, CMOS VLSI…
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▼ As process technology advances into Very Deep Sub-Micron (VDSM) level, CMOS VLSI system reliability is becoming a major concern. One of the main causes of reliability reduction is caused by charge particle strikes due to cosmic radiation which create soft errors, also referred to as Single Event Upsets (SEUs). In past technologies, this problem was limited to radiation hostile environments such as space. With VDSM designs, however, low energy particles at the ground level can cause soft errors, making CMOS circuits sensitive to atmospheric neutrons, as well as to alpha particles created by the unstable isotopes that can be found in materials of a chip. Soft errors are a major problem in mission critical applications where reliability is the main concern over performance and cost, such as heart defibrillators, avionics, etc. Our research focus is to provide design and analysis methodologies that reduce soft error in CMOS VLSI circuits implemented in nanometer process technologies. From the designer's point of view, a VLSI system consists of combinatorial logic, memory, and clock networks. We propose several design and analysis methodologies to reduce soft errors in logic, memories (SRAM), and clock networks. For logic, we pursue two different tracks: 1) Nodes sensitivity analysis and mitigation for soft errors in CMOS logic. 2) Soft Delay errors effects and analysis. For memories, we have developed an efficient Built-in Current Sensor (BICS) for the detection and localization of SEUs. We use a combination of BICS and ECC for single as well as multiple errors correction in SRAM. For the clock networks, we have analyzed the radiation-induced clock jitters and race. Our results for various test circuits show that the accuracy achieved by our analysis approaches is close to Spice and, at the same time, they are several orders of magnitude faster than Spice. We reduced the sensitivity of nodes by applying electrical hardening technique on highly sensitive nodes which were determined by our approaches. The reliability analysis of our new BICS shows that it can work under process, voltage, and temperature variations as well as in harsh noise environments.
Advisors/Committee Members: Papachristou, Christos A.
Keywords: nanometer, SEU, SMU, Soft errors, Soft Delay, BICS, Clock jitters, race, radiation, neutron, alpha-particles
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11.
Guo, Zhihao.
INTELLIGENT MULTIPLE-OBJECTIVE PROACTIVE ROUTING IN MANET WITH PREDICTIONS ON DELAY, ENERGY, AND LINK LIFETIME.
Degree: PhD, Computer Engineering, 2008, Case Western Reserve University
► In this dissertation we develop an intelligent multiple objective routing mechanism that…
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▼ In this dissertation we develop an intelligent multiple objective routing mechanism that can be integrated with any MANET proactive protocol. Our system considers three routing objectives: minimizing average end-to-end delay, maximizing network energy lifetime, and maximizing packet delivery ratio. Our system measures and predicts on multiple dynamic network conditions including queuing delay, energy consumption, and link lifetime. Based on the predicted values, our system calculates multiple routing metrics including queuing delay, energy cost, and link stability cost, and updates the routing table with evaluation of these routing metrics. This dissertation is divided into three parts, part 1 and part 2 are dedicated to the exclusive handling of the metric of queuing delay and the metric of energy cost respectively, compositive handling of all three metrics are investigated in the part 3. These three parts are formatted as three independent papers. Multiple prediction methods are developed. Two optional types of feedforward neural network models, Multi-Layer Perceptron (MLP) and Radial Basis Function (RBF), are used for queuing delay prediction in part I.; Autoregressive Integrated Moving Average (ARMIMA) are used for energy consumption prediction in part II; and double exponential smoothing is used for predicting both queuing delay and energy consumption in part III. Residual link lifetime is estimated using a heuristic of the pattern of link lifetime variation derived from the normal-like distributions of the link lifetimes in typical MANET mobility scenarios. In all the three parts, our system is integrated into OLSR, which is a well-known proactive MANET routing protocol. The regular topology control message exchange in OLSR is extended to convey the values of routing metrics. Our system uses a novel routing table computation algorithm called TierUp that evaluates node-state routing metrics (e.g., queuing delay) with reduced computational complexity compared to Dijkstra’s algorithm. Through extensive ns2 simulation our extended version of OLSR is capable of substantially improve the adaptability to the network dynamics and therefore achieve significant performance improvements in terms of all the three routing objectives. More over, our extended version of OLSR enables the routing decision maker to effectively set different preferences to different routing objectives.
Advisors/Committee Members: Malakooti, Behnam.
Keywords: OLSR_NN; OLSR_EA; OLSR_MO; multi-objective proactive MANET routing; TierUp; neural network; Multi-Layer Perceptron (MLP); Radial Basis Function (RBF); ARIMA; double exponential smoothing; normalized weighted utility function
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12.
Harmanani, Haidar M.
Resource allocation and reallocation techniques in high-level synthesis with testability constraints.
Degree: PhD, Computer Engineering, 1994, Case Western Reserve University
► The increase in density that the advent of Very Large Scale Integration…
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▼ The increase in density that the advent of Very Large Scale Integration (VLSI) has allowed, made the move to higher levels of design abstraction imperative. High Level Synthesis emerged as a result; however, most solutions (1) were not optimal; (2) did not incorporate testing at the system level. In this Work, we propose a prototype high-level synthesis system with self-testability, SYNTEST, that alleviates the above problems. SYNTEST is based on a model that treats testing as a structural design property during data path allocation. Thus, the design is testable by construction and there is no need for the traditional post-design test insertion methods. The most significant aspect of this work is that it covers the void between the fields of high-level synthesis and design for testability. This allows to exploit the tight relation that exists between both disciplines in an integrated system level design environment. The allocation method incorporates a test points (registers) selection method which trades test overhead for fault coverage. We follow the allocation method with a reallocation method which aims at exploring any possible design improvements which may be due to the non-optimal nature of the design process. By considering placement and routing, in addition to compon ent cost, the reallocation modifications become more effective and more realistic. Another motivation for the reallocation process is that it may be desirable to reuse the old data path in order to generate an alternate structure under a different technology. Thus, the designer may reuse the old structure to generate a new one, optimized under a different cost function. The reallocation phase is based on a rip-and-rebind approach. Finally, we automatically generate VHDL output from SYNTEST in order to complete the silicon compilation iteration. The output is a mixed behavioral and structural VHDL description of a testable data path and a controller. We link SYNTEST to the COMPASS Design Automation tools, through VHDL, which serves as our means to validate our design model and architecture. We validate our approach using various design and benchmark examples and several chips layouts were generated.
Advisors/Committee Members: Papachristou, Christos A.
Keywords: Resource allocation; reallocation techniques; high-level synthesis; testability constraints
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13.
Harous, Saad.
Studies in distributed simulation.
Degree: PhD, Computer Engineering, 1991, Case Western Reserve University
► Performance study of modern computer and communication systems critically depends on our…
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▼ Performance study of modern computer and communication systems critically depends on our ability to simulate them with reasonable speed, since these systems are often mathematically intractable. Simulation on a uniprocessor is often unacceptably slow. A promising alternative is distributed simulation, i.e., simulating the system on a distributed system of processors that communicate with each other via messages. Several distributed simulation schemes (Chandy79b), (Chandy81), (Jefferson82) have been proposed in literature; but their performance is not well understood. Our Goal in this thesis is to study distributed simulation of various classes of systems. This thesis consists of two parts. In the first part, we have developed a new approach to study the performance of distributed simulation. This approach throws light on the relationship between overhead and performance, and defines more realistic notions of ideal speedup. We have done extensive simulation study of two well known distributed simulation schemes (Chandy79b), (Chandy81) using this approach, with interesting results regarding the above issues. In the second part, we have developed a model of Timed Petri Nets which is more general than known models in terms of modeling convenience. Also, we have presented an approach towards distributed simulation of this model.
Advisors/Committee Members: Kumar, Devendra.
Subjects: Computer Science
Keywords: Distributed simulation
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14.
Hearn, Jonathan.
COMPETITIVE MEDICAL IMAGE SEGMENTATION WITH THE FAST MARCHING METHOD.
Degree: MS, Computer Engineering, 2008, Case Western Reserve University
► Extensions to the fast marching method are introduced with the aim of…
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▼ Extensions to the fast marching method are introduced with the aim of further automating the segmentation of medical image data. A competitive algorithm is used to minimize the occurrence of bleeding across boundaries, and techniques including automatic starting point selection, statistical region combination, and user-influenced region expansion are introduced to support the competitive paradigm. Results show good performance in a variety of scenarios, with poorer performance in the presence of high-intensity noise and unusually obscure boundaries.
Advisors/Committee Members: Cavusoglu, M. Cenk.
Keywords: Fast Marching Method; Level set Method; Image Segmentation; MRI; Competitive
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15.
He, Xiaoping.
Methods for an expert system to access an external database.
Degree: PhD, Computer Engineering, 1991, Case Western Reserve University
► This dissertation develops several methods by which an expert system can intelligently…
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▼ This dissertation develops several methods by which an expert system can intelligently access an external database. The motivation for this research came from an advanced manufacturing application which required fairly sophisticated reasoning about a relatively large volume of factual knowledge which is stored in an external database. An expert system was designed and implemented to do this in a relatively efficient way which takes advantage of contemporary database and logic programming technologies. An interesting feature of this design is its use of meta-interpreters to engineer the system's software; i.e., a meta-interpreter was used to generate database queries when information from the external database was needed. Although this expert system provided a practical solution, it also suggested that a more conceptual solution would be advantageous. A more powerful inference engine would remove the need for some of the specialized software that was part of the expert system and at the same time would allow the expert system rules to be more declarative. The main feature of this new inference engine is that it performs a graph search; i.e., when attempting to solve a subgoal, it uses all possible answers from previously solved subgoals. Since the subgoals are essentially Prolog subgoals, in general there will be a set o f answers for each subgoal. The basic problem which must be solved is that two subgoals may have a number of answers in common, but each may also have answers which are not answers to the other because neither subgoal is a substitution instance of the other. We have developed a solution to this problem and incorporated it into a method which performs a graph search of a space defined by a logic program and a goal. We prove that this method is both sound and complete.
Advisors/Committee Members: Ernst, George W.
Subjects: Artificial Intelligence
Keywords: expert system external database
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16.
Hwang, Suntae.
VLSI testing for high reliability: Mixing IDDQ and logic testing.
Degree: PhD, Computer Engineering, 1993, Case Western Reserve University
► Recently, it has been recognized that logic testing does not detect many…
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▼ Recently, it has been recognized that logic testing does not detect many physical defects such as bridging and open faults. In this study, we examine the effectiveness of combined logic and Iddq testing to detect stuck-at and bridging faults. The stuck-at faults are detected by logic testing by voltage measurement and Iddq testing detects bridging faults. Near-minimal stuck-at test sets are used for this combined logic and Iddq test environment. These near-minimal stuck-at test sets are generated using standard test programs, while using collapsed fault lists. We examined ISCAS '85 and ISCAS '89 benchmark circuits. A comparison is given for the fault coverage obtained under this combined test environment with other studies based on pure logic test and Iddq test. Also, the results of Iddq-based test sets (vectors generated specifically for Iddq testing) are compared with those of stuck-at test sets. To save the test effort, we also examine the bridging fault coverage in Iddq testing when partial stuck-at test sets are used. We present a case study on a microprogrammed processor using a functional test set in the combined test environment to detect logic and bridging faults. Based upon results obtained during this study, we established a relationship between stuck-at test sets and bridging fault coverage in Iddq testing, and finally, we suggest a guideline on the use of stuck-at test sets in Iddq environment.
Advisors/Committee Members: Rajsuman, Rochit.
Keywords: VLSI testing; reliability; IDDQ; logic testing
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17.
Kim, Hwa-Soo.
A large-grain mapping approach for multiprocessor systems through data flow model*.
Degree: PhD, Computer Engineering, 1991, Case Western Reserve University
► This dissertation presents a large-grain level mapping method of numerical-oriented applications onto…
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▼ This dissertation presents a large-grain level mapping method of numerical-oriented applications onto multiprocessor systems. The method is based on the large-grain data flow representation of the input application and it assumes a general interconnection topology of the multiprocessor system. We use the large-grain data flow model because such representation best exhibits inherited parallelism in many important applications, e.g., CFD models based on partial differential equations can be represented in large grain data flow format, very effectively. We consider a generalized interconnection topology of the multiprocessor architecture, including such architectural issues as interprocessor communication cost, with the aim to identify the "best matching" between the application and the multiprocessor structure. The overall objective is to minimize the total execution time of the input algorithm running on the target system. The mapping strategy consists of the following steps: (1) Large grain data flow graph generation from the input application using compilation techniques. (2) Data flow graph partitioning into basic computation blocks. (3) Physical mapping onto the target multiprocessor using a priority allocation scheme for the computation blocks. The proposed method is applicable to the parallel solution of complex Computational Fluid Dynamics (CFD), particularly CFD problems using a large number of partial differential equations (PDEs). Our approach achieves automatic parallelization of the PDEs involved by detecting their complex data dependencies, segmenting the PDEs into PDE blocks, and providing a cost-effective scheduling of the PDE blocks onto the target multiprocessor architecture. The several numerical-oriented application algorithms, such as differential equations, rotating shaft problems, 2-D Navier Stokes equations, etc., have been used as the testing inputs. The experimental results are analyzed with respect to time-steps required, number of data transfer, speedup, efficiency, and load-balance. These results are very encouraging. ftn*This work is partially supported by NASA Lewis Research Center under grant number: NAG3-1103
Advisors/Committee Members: Papachristou, Christos A.
Subjects: Computer Science
Keywords: Large-grain mapping; Multiprocessor systems
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18.
Kovacic, Kathy Jeanne.
Using common-sense knowledge for computer menu planning.
Degree: PhD, Computer Engineering, 1995, Case Western Reserve University
► Menu planning is a complex problem requiring both expert and common-sense knowledge.…
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▼ Menu planning is a complex problem requiring both expert and common-sense knowledge. The common-sense aspect is the description of what a menu should look like, and how substitutions can or should be made. A framework for representing this information is presented; the structure contains separate layers for foods, dishes, meals, and menus, and means for relating the layers to one another. Implementations of this framework are presented, with results and analysis. A vocabulary for common sense in menu planning is proposed.
Advisors/Committee Members: Sterling, Leon.
Subjects: Computer Science
Keywords: Computer menu planning
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19.
Krishnamurthy, Sivasubramaniam T.
STATIC TIMING ANALYSIS OF MICROPROCESSORS WITH EMPHASIS ON HEURISTICS.
Degree: MS, Computer Engineering, 2008, Case Western Reserve University
► As designers build complex digital circuits with ever diminishing device sizes, there…
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▼ As designers build complex digital circuits with ever diminishing device sizes, there is a need to obtain fast circuits with low hardware overhead. Critical path is the longest sensitizable path in a digital logic circuit which determines the operating frequency of the circuit. Static timing analyzers enumerate critical paths in a circuit and determine the optimal operating frequency. This work presents a static timing analyzer that makes use of an ATPG technique based on the PODEM engine. To improve the efficiency of the technique, a partitioning scheme is used in the path sensitization subroutine to reduce the search space. The results from this implementation for the ISCAS ’85 and ’89 benchmarks demonstrates performance improvements.
Advisors/Committee Members: Saab, Daniel G.
Keywords: Static Timing Analysis, Partitioning, Heuristics, Microprocessors, Digital Logic, VLSI
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20.
Lakhotia, Arun.
A workbench for developing logic programs by stepwise enhancement.
Degree: PhD, Computer Engineering, 1990, Case Western Reserve University
► Logic programming languages provide a higher level of data and control abstraction…
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▼ Logic programming languages provide a higher level of data and control abstraction compared to procedural languages. The greater abstraction has made visible some new patterns in programs and in the process of their construction. Programs may be conceived of containing a skeleton program that provides its primary flow of control. A program is developed by adding computation around its skeleton without altering the control flow it provides. This is called enhancement and is manifested by the addition of extra arguments and goals in a program. Stepwise enhancement takes advantage of this decomposition of a program into skeleton and enhancements. It is a method of programming that suggests the development of programs by first constructing a skeleton program that provides its main flow of control. The final program is constructed by applying a sequence of enhancements to this skeleton. Further, if the successive enhancements are mutually independent the development of program is forked into independent branches. The resulting programs are composed into one at a later stage. This incremental method of programming provides a new way for separating concerns during programming. It also identifies the need for additional support from a programming environment to aid in the process of constructing programs. The workbench designed in this th esis is equipped with the support necessary for developing logic programs by stepwise enhancement. It provides a mechanical aid to perform enhancements. It also provides tools to compose programs that result from parallel but independent enhancements of the same program. The enhancement and composition tools use program transformation techniques for carrying out the respective operations. This use of program transformations contrasts with their conventional use to improve the efficiency of programs.
Advisors/Committee Members: Sterling, Leon S.
Subjects: Computer Science
Keywords: workbench developing logic programs stepwise enhancement
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21.
Lee, Sungkoo.
A constraint-based 2-dimensional object display system.
Degree: PhD, Computer Engineering, 1991, Case Western Reserve University
► This thesis will discuss a system for automatic layout and display of…
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▼ This thesis will discuss a system for automatic layout and display of 2-D objects. Our goal is to be able to display data of executing programs. We want the system to be usable with common higher-order languages such as C, and to require no modification of the source program. We give the textual descriptions of the special objects with some rules or constraints and we derive several layout algorithms from the textual descriptions for how they should be displayed on the screen. Constraints are a useful tool to represent the relations that must be maintained between objects. They can be used to specify relations between objects, to maintain consistency between user program data structures and graphical depiction of objects, and to specify layout. This system can be used to quickly create visual displays of information in a program, and can be applied to a visual debugger or some graphical drawing system, and has been implemented on a Unix systems in Prolog and C languages.
Advisors/Committee Members: Radack, Gerald M.
Keywords: constraint-based; 2-dimensional object; display system
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22.
Li, Jianchun.
DESIGN OF AN FPGA-BASED COMPUTING PLATFORM FOR REAL-TIME 3D MEDICAL IMAGING.
Degree: PhD, Computer Engineering, 2005, Case Western Reserve University
► Real-time 3D medical imaging requires very high computational capability that is beyond…
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▼ Real-time 3D medical imaging requires very high computational capability that is beyond most of the general computing platforms. Although application specific integrated circuits (ASIC) can provide solutions for a particular algorithm, they are too expensive to develop and most of them are not flexible enough to adapt to the evolution of existing algorithms or the emergence of new problems. FPGA-based reconfigurable architectures combined with general-purpose processors exhibit a good tradeoff in performance and flexibility, and are affordable for practical applications. To address the problems in designing such a system, including long designing and testing time, complex data manipulation and high performance requirement etc., we designed a new computing platform to accelerate a broad range of local operation-based 3D medical imaging algorithms. This platform is composed of a new data caching scheme, called brick caching scheme and a reconfigurable System-on-Chip (SoC) architecture targeted to Xilinx Virtex-II Pro FPGAs. The brick caching scheme exploits spatial locality of reference in three dimensions with 3D block caching; it enables data prefetching by obtaining input data block information through input-output space mapping; it also supports multiple data accesses with data duplication. An intelligent data caching system is built around a PowerPC processor core in the SoC architecture to support the brick caching scheme. A multiple pipeline execution unit that is reconfigurable to different algorithms is designed to perform vectorized computation. Two algorithms are implemented and tested on this platform, one is the FDK cone-beam CT reconstruction algorithm and the other is the mutual information-based 3D registration algorithm. Our simulation results demonstrate that a speed-up of about 30 can be achieved for both of the algorithms.
Advisors/Committee Members: Papachristou, Christos.
Keywords: Medical imaging, FPGA, Computing platform, FDK reconstruction, mutual information, 3D registration
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23.
Lin, Fuyau.
An integration of logic and functional programming paradigms: Type theory and meta-narrowing.
Degree: PhD, Computer Engineering, 1991, Case Western Reserve University
► Programmers involved in software designs, frequently feel the need of the co-existence…
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▼ Programmers involved in software designs, frequently feel the need of the co-existence and collaboration of different description notations, e.g., predicate logic and functions. The aim of this thesis is the design and the realization of a programming language in which a functional language and Horn clauses are integrated in a single framework. The central idea of our approach is to use typed lambda-calculus and meta-narrowing. Meta-narrowing is based on the flat SLD-resolution. The implementation of our system is to be considered an experimental tool, named LL. This language extends logic language by adding the function capability and types and replacing the heart of the unification process by narrowing. This thesis presents the descriptions of this language and illustrates its capabilities. We also summarize the diverse approaches that suggest their integrations at different levels.
Advisors/Committee Members: Hunt, Frances E.
Subjects: Computer Science
Keywords: logic functional programming paradigms
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24.
Lou, Yanjun.
On integration of object-oriented features with deductive data language.
Degree: PhD, Computer Engineering, 1992, Case Western Reserve University
► Integrating value-oriented and object-oriented data models is one of the active research…
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▼ Integrating value-oriented and object-oriented data models is one of the active research directions in database field. In this thesis, we first discuss the properties of an object-oriented data model that combines the simplicity of relational data model and features of object-oriented data models. Meta variables are introduced for information hiding, data abstraction, and type inheritance. Partial order is defined on classes as well as on types to describe inheritance relationship. The concept of named values bridges the concepts of values in logical models and objects in object-oriented models. With union values, values can be formed from its subset values. Semantics and key features of the model are also discussed. Next, we consider Horn clause programs from an object-oriented perspective. Current Horn clause languages (Prolog/Datalog) do not have the concept of methods and there is no polymorphism. However, their declarative paradigm and formal theory have won enormous popularity. Our observation is that Horn clause languages can be extended and object-oriented features can be integrated with the support of our data model. Based on this observation, we present a rule-based deductive data language, LLO, which has object-oriented features such as object identities, polymorphism and encapsulation. Methods are defined by rules and method inhe ritance is achieved through typing and unification mechanisms. Datalog and nested relational models are shown to be subsets of LLO. Semantics of the language is analyzed and LLO as a full-fledged programming language are addressed. A formalization of the subset semantics is given and some results of fixpoint semantics of LLO programs are presented.
Advisors/Committee Members: Ozsoyoglu, Z. Meral.
Subjects: Computer Science
Keywords: integration object-oriented features deductive data language
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25.
Masri, Wassim.
DYNAMIC INFORMATION FLOW ANALYSIS, SLICING AND PROFILING.
Degree: PhD, Computer Engineering, 2005, Case Western Reserve University
► Dynamic information flow analysis is concerned with the runtime monitoring and regulation…
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▼ Dynamic information flow analysis is concerned with the runtime monitoring and regulation of the flow of information among objects throughout a system and ultimately between the system and the outside world. A new approach to dynamic information flow analysis is presented that can be used to detect and debug insecure flows in programs. It can be applied offline to validate and debug a program against an information flow policy, or, when fast response is not critical, it can be applied online to prevent illegal flows in deployed programs. Dynamic mechanisms are inherently unable to detect implicit information flows; our approach incorporates an optional static preprocessing phase that identifies implicit flows and transforms them into explicit ones. The resulting hybrid mechanism is therefore capable of detecting both explicit and implicit information flows. Program slicing is an integral part of debugging against an information flow policy. Forward computing slicing algorithms, which do not require a previously stored execution trace, are especially suited for interactive debugging. This dissertation proposes a dynamic slicing algorithm, which is characterized as forward computing, precise and applicable to unstructured programs. Observation-based testing (OBT) is an approach in which executions of a program are profiled and then analyzed using cluster analysis and sampling methods to identify unusual or suspicious executions for manual auditing. This technique can be used to detect ordinary failures as well as intrusive behaviors. It can also be the basis for test-case filtering. This dissertation contributes to observation-based testing research by devising two profiling techniques that capture a relatively higher level of detail from a program execution namely, information flow profiling and slice profiling. In order to empirically verify their relative efficiency, we used them as well as other types of profiles such as function calls and data flow profiles to conduct test-case filtering experiments. The test-case filtering experiments involved OBT techniques as well as coverage-based techniques. The comparative results are presented and discussed. Finally, this dissertation presents a prototype tool for detecting and debugging insecure information flows in Java byte programs, it is also capable of generating information flow and slice execution profiles.
Advisors/Committee Members: Podgurski, Andy.
Subjects: Computer Science
Keywords: INFORMATION FLOW; addFlow; CDSTACK; InfoFlow; Implicit flows; DDynCD; Java
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26.
McMichael, Scott Thomas.
Lane Detection for DEXTER, an Autonomous Robot, in the Urban Challenge.
Degree: MS, Computer Engineering, 2008, Case Western Reserve University
► This thesis describes the lane detection system developed for the autonomous robot…
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▼ This thesis describes the lane detection system developed for the autonomous robot DEXTER in the 2007 DARPA Urban Challenge. Though DEXTER was capable of navigating purely off of GPS signals, it often needed to drive in areas where GPS navigation could not be trusted completely. In these areas it was necessary to use a method of automatically detecting the lane of travel so that DEXTER could drive properly within it. The developed system functions by merging the outputs of a number of independent road detection modules coming from several sensors into a single drivable output path. This sensor derived path is compared with the map derived path in order to produce an optimal output based on the relative confidences of the two information sources. The full lane detection system is able to adaptively drive according to the best information source and perform well in a variety of diverse driving environments.
Advisors/Committee Members: Newman, Wyatt S.
Keywords: autonomous robot, DARPA Urban Challenge, lane detection, road detection, computer vision, sensor fusion
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27.
Nourani-Dargiri, Mehrdad.
Area and delay estimation for constraint-driven high-level synthesis.
Degree: PhD, Computer Engineering, 1994, Case Western Reserve University
► The flurry of activity in high level synthesis and its increasing popularity…
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▼ The flurry of activity in high level synthesis and its increasing popularity as a research topic, both in industry and academia, is a natural consequence of the progress in VLSI design technology and methodology. High level synthesis (HLS) fills the gap between behavioral level and layout level by automatically generating an RTL datapath realization from a behavioral description. The actual circuit layout can be generated later from the RTL datapath using a silicon compiler. A common characteristic of most HLS systems is the lack of consideration to the logic and layout synthesis aspects during the HLS process. The designs generated by these systems may or may not satisfy the initial design requirements and thus the design may need to be changed or modified. One method to address this deficiency is to use estimators, as a bridge between high and low levels, during HLS. The estimators can be iteratively invoked at high levels (e.g. scheduling and allocation) to provide a guiding mechanism to search the design space, which in turn leads to improved design quality and shorter design turnaround time. Motivated by the above observations, in this dissertation we present methods to cover the gap between high and low levels of design hierarchy, including: (1) Scheduling and mixed scheduling-allocation algorithms under time and resource constraints based on Liapunov stability theorem; (2) A neural network based scheduling as an alternative for implementing on parallel machines; (3) A layout estimation method which uses non-probabilistic analytical formulas in a constructive algorithm to estimate the overall area of a datapath; (4) A delay estimation algorithm which identifies false paths at the RTL and computes the static and dynamic critical delay in a datapath. Incorporation of these tools into an experimental HLS system, SYNTEST, has been completed with the overall objective of generating a structural VHDL description of a self-testable RTL datapath from a given behavioral VHDL specification.
Advisors/Committee Members: Papachristou, Christos A.
Keywords: constraint driven synthesis
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28.
Nygate, Yossi Aharon.
ASPEN: Structuring design of complex knowledge-based systems.
Degree: PhD, Computer Engineering, 1994, Case Western Reserve University
► ASPEN is a new approach for developing complex, knowledge based, problem solving…
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▼ ASPEN is a new approach for developing complex, knowledge based, problem solving systems. The essence of ASPEN is to decompose programs into five consecutive, well integrated, problem solving stages: Abstraction, Synthesis, Planning, Execution and moNitoring. The five stages of ASPEN are a natural decomposition common to many problems and are applicable for a wide variety of systems. ASPEN is particularly suitable for integrating meta-programming techniques and for problems where plans may fail during execution due to changing knowledge. ASPEN provides an original perspective on the coding task. It describes a common-sense division of a complex problem into logical components and how they are linked together to provide an overall solution. Each component uses a knowledge representation and problem solving technique that is best suited to the problem domain. The interaction between the stages is through knowledge representation transformations and feedback. The stages of ASPEN are developed separately, though tightly integrated. The output of abstraction forms the input of synthesis, as does the output of planning for execution and monitoring. When failures occur, information flows back from monitoring to planning, synthesis and abstraction. ASPEN compromises between the use of sing le or multiple problem solving methods by providing a structured decomposition that allows each stage to use different knowledge based techniques while defining a set number of modules with well delimited borders and functionalities. This thesis describes ASPEN and how I implemented each of its stages both in a Bridge playing program and a telecommunications application developed by me at ATandT. The Bridge playing program exhibits many characteristics of good human players and, to our knowledge, is better than any other similar program. The telecommunications network management application is currently fielded at Regional Bell Operating Companies throughout the U.S. and overseas. ASPEN has proven to be a reusable, robust, and reliable design method as seen in the success of two knowledge based systems that greatly benefited from using the structured decomposition of this new approach.
Advisors/Committee Members: Sterling, Leon.
Subjects: Computer Science
Keywords: ASPEN Structuring design complex knowledge based systems
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29.
Ou, Jen-Chieh.
HARDWARE DESCRIPTION LANGUAGE PROGRAM SLICING AND WAY TO REDUCE BOUNDED MODEL CHECKING SEARCH OVERHEAD.
Degree: PhD, Computer Engineering, 2007, Case Western Reserve University
► Modern complex digital systems are described in Hardware Description Language (HDL). The…
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▼ Modern complex digital systems are described in Hardware Description Language (HDL). The increase in design complexity is causing verification tools to require large amount of resources. In this research, we present a program slicing technique to extract statements from an RTL design that directly or indirectly contribute to a formal verification rule. The extracted statements constitute a less complex design that reduces the resource needed by verification tools without compromising the quality of the result. Both static and conditioned Verilog slicer is implemented in a computer program that is used as a pre-processor to SAT-based bounded model checker SMV and ATPG-based bounded model checker Formal. We show experimentally that the resources of the formal verification tool in terms of both CPU and memory are reduced significantly when verifying the USB2.0 IP core. The proposed slicer is the first hardware slicing technique that handles inter-module signal dependency in a hierarchical Verilog design environment.
Advisors/Committee Members: Saab, Daniel.
Keywords: Slicing; veriï¬cation; Program Slicing; Verilog; RTL
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30.
Qiang, Qiang.
FORMAL: A SEQUENTIAL ATPG-BASED BOUNDED MODEL CHECKING SYSTEM FOR VLSI CIRCUITS.
Degree: PhD, Computer Engineering, 2006, Case Western Reserve University
► Bounded Model Checking (BMC) is a formal method of verifying Very Large…
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▼ Bounded Model Checking (BMC) is a formal method of verifying Very Large Scale Integrated (VLSI) circuits. It shows violation of a given circuit property by finding a counter-example to the property along bounded state paths of the circuit. The BMC problem is inherently NP-complete and is traditionally formulated to a boolean SATisfiability (SAT) problem, which is subsequently solved by a SAT solver. Automatic Test Pattern Generation (ATPG), as an alternative to SAT, has already been shown an effective solution to NP-complete problems in many computer-aided design areas. In the field of BMC, ATPG has already achieved promising results for simple properties; its effectiveness for more complicated nested properties, however, remains unknown. This thesis presents the first systematic framework of ATPG-based BMC capable of checking properties in all nested forms on gate level. The negation counterpart to a property is mapped into a structural monitor, which is tailored to a flattened model of the input circuit. A target fault is then injected at the monitor output, and a modified ATPG-based state justification algorithm is used to search a test for this fault. Finding such a test corresponds to formally establishing the property. The framework can easily incorporate any existing ATPG tool with little modification. The proposed framework has been implemented in a computer program called FORMAL, and has been used to check a comprehensive set of properties of GL85 microprocessor and USB 2.0 circuits. Experimental results show that the ATPG-based approach performs better in both capacity and efficiency than the SAT-based techniques, especially for large bounds and for properties that require large search space. Therefore, ATPG-based BMC has been demonstrated an effective supplement to SAT-based BMC in VLSI circuit verification.
Advisors/Committee Members: Saab, Daniel G.
Keywords: Bounded Model Checking, BMC, Automatic Test Pattern Generation, ATPG, Sequential ATPG, Formal Verification, Functional Verification, VLSI Design and Verification
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